Engineer System
Resume:
Praveen Kumar T
e-mail: **************@*****.***
mob: +91-897*******
Professional Summary:
> Working as Tech Lead at Shri Bajrang Industries PVT LTD, Delhi
> Experience in working with various FPGA and micro controller devices
> Good knowledge in programming HDL
> RTL simulation and test bench creation
> Good knowledge in Hardware design
> Floor plan/place in FPGA devices
> Test design and implementation
> Customer Support
> 5 years experience as design engineer and also experience in embedded
software for testing peripherals
> Good team player and ability to adapt to new technologies
> Proven ability to work under pressure
Skill Summary:
> Programming : Embedded C, Verilog HDL, VHDL.
> FPGA devices worked: Altera, Lattice, and Actel.
> Microcontrollers : Microchip PIC32, Stmicro STM32F series
> Hardware design tool : Or-Cad-Capture Cis
> Operating system : windows
> Development Tools : Lattice ispLEVER,LatticeMico32 MSB,Altera
quartus2,Nios2 for
Eclips,Actel Libero IDE,Mentor
Graphis modelsim,
matlab
Work Experience:
Working as Hardware engineer in Shri Bajrang Industries Pvt.Ltd, Delhi
since last 7 months to till date. Strong digital design skills and
experience in verilog RTL coding. Experience in designing hardware.
Education:
> Post graduation in Electronics 2007 pass out from Osmania University
> Bachelor degree in Maths, physics chemistry (MPC) 2005 pass out from
Osmania University
Projects Details
1. INTEGRATED PASSENGER INFORMATION SYSTEM (IPIS)
For First version of IPIS
Languages : Embedded C & Verilog HDL
Role : Involved in Hardware design, RTL coding,
Documentations
Cross Platform: Microchip PIC32
Tools & FPGA: Lattice ispLEVER, Actel Libero IDE9.1
The FPGA device used is Lattice LFXP2-8E
144 TQFP package, Actel
ProAsic3nano100pin
For Second version of IPIS
Languages : Embedded C & Verilog HDL
Role : Involved in Hardware design, RTL coding,
Testing peripherals by writing software
coding and Documentations
Cross Platform: Nios9.0 & Nios 9.1 with Eclips environment
Tools & FPGA: Quartus2 9.1, nios9.1 modelsim for
Simulation testing. The
FPGA used is
Cyclone3 EP3C10 EQFP
144 package
For Third version of IPIS
Languages : Verilog HDL
Role : Involved in Hardware design, RTL coding,
and Documentations
Cross Platform: STMicro STM32F series ARM processor
Tools & FPGA: Lattice ispLEVER,The FPGA device used
is Lattice LFXP2-8E 144 TQFP package
Description:
The Project involves the implementation of Display system which includes
passenger information like train information, coach guidance, PC based
announcement system. The system involves various display boards,
Communication Hubs. The chosen Microcontroller is Atmel's
AT89S8253/PIC32/STM32F series and Lattice xp2 series & Altera cyclone3
series. This system is user friendly and provided different features as
much needed in the railways as per RDSO Specifications. This system is
controlled by C.C.U which the running database is redundant with another
C.C.U in power failure conditions, so that the data can be stored forever
until and unless the system is destroyed.
This INTEGRATED PASSENGER INFORMATION SYSTEM is Approved by RDSO as per
standards
2. Digital Output Solid state relay board(DOSSR32)
Languages : Verilog HDL
FPGA used : Lattice LFXP2-5E-5QN208I.
Description:
The DOSSR32 board is part of the ECIL-PLC system and it is based on ADISO-
3000 bus. This board can drive maximum of 32 output filed devices. This
board will be designed based on FPGA and replaces existing DOSSR32, built
based on discrete and logic devices, without modifying the existing
software. This board operates in different modes and one of the mode is
same as existing board functionality.
The DOSSR32 is an isolated Digital output board, electrically and
mechanically compatible with ADIOS-3000 bus. The ADIOS bus based DOSSR32
board drives output devices. The output device that shall operate on 60V,
1A (max) shall be interfaced with this board. The DOSSR32 board consists of
32 channels, in other words this board can drive maximum of 32 output
devices. The data written by the CPU controller card will be latched and
available on one of the EURO connector (P2) to drive the devices.
Isolation provided by means of solid state relays. The channel status, bus
access and fault indication will be provided by front panel LED's. The
output protection will be provided through 500mA resettable fuses. The
DOSSR32 will be designed to operate in MODE0, MODE1, MODE2 and MODE3
The main features of the DOSSR32 board as follows
. 32 identical solid state driver outputs
. Short circuit/overload protection for individual channel
. Software readability of board type and slot address
. Board access status indication
. Feedback of output data
. Fault status indication
. Channel status indications
3. Digital Output Electro Magnetic Relay board (DOEMR)
Languages : Verilog HDL
FPGA used : Lattice LFXP2-5E-5QN208I.
Description:
The DOEMR board is part of the ECIL-PLC system and it is based on ADISO-
3000 bus. This board can drive maximum of 32 output filed devices. This
board will be designed based on FPGA and replaces existing DOEMR, built
based on discrete and logic devices, without modifying the existing
software. This board operates in different modes and one of the mode is
same as existing board functionality.
The DOEMR is an isolated Digital output board, electrically and
mechanically compatible with ADIOS-3000 bus. The ADIOS bus based DOEMR
board drives output devices. The output device that shall operate on 60V,
1A (max) shall be interfaced with this board. The DOEMR board consists of
32 channels, in other words this board can drive maximum of 32 output
devices. The data written by the CPU controller card will be latched and
available on one of the EURO connector (P2) to drive the devices.
Isolation provided by means of magnetic relays. The channel status, bus
access and fault indication will be provided by front panel LED's. The
output protection will be provided through 500mA resettable fuses. The
DOEMR will be designed to operate in MODE0, MODE1, MODE2 and MODE3.
The main features of the DOEMR board as follows
. 32 identical magnetic driver outputs
. Short circuit/overload protection for individual channel
. Software readability of board type and slot address
. Board access status indication
. Feedback of output data
. Fault status indication
. Channel status indications
4. Digital input board(DIFF32)
Languages : Verilog HDL
FPGA used : Lattice LFXP2-5E-5QN208I.
Description:
The DIFF32 board is part of the ECIL-PLC system and it is based on ADISO-
3000 bus. This board can accepts maximum of 32 output filed devices. This
board will be designed based on FPGA and replaces existing DIFF32, built
based on discrete and logic devices, without modifying the existing
software. This board operates in different modes and one of the mode is
same as existing board functionality.
The DIFFR32 is a Digital input board, electrically and mechanically
compatible with ADIOS-3000 bus. The ADIOS bus based DIFF32 board accepts
outside filed devices. The outside devices that shall operate on 60V, 1A
(max) shall be interfaced with this board. The DIFF32 board consists of 32
channels, in other words this board can accepts maximum of 32 outside
devices. The data coming from outside field will be latched and available
on one of the EURO connector (P2).The channel status, bus access and fault
indication will be provided by front panel LED's. The channel output
protection will be provided through 500 mA resettable fuses. The DIFF32
will be designed to operate in MODE0, MODE1 and MODE2
The main features of the DIFF32 board as follows
. Software readability of board type and slot address
. Board access status indication
. Feedback of output data
. Fault status indication
. Channel status indications
5. Presently working True Colour Video-cum-Train Information Display
System
Languages : Embedded C & Verilog HDL
Role : Involving in Hardware design, RTL coding,
Testing peripherals by writing software
coding and Documentations
Cross Platform: Nios9.0 & Nios 9.1 with Eclips environment
Tools & FPGA: Quartus2 9.1, nios9.1 modelsim for
simulation testing. The
FPGA used is
cyclone3
Description:
True Colour Video -cum- Train Information Display System gives the train
arrival/departure information and any other video to passengers. It
specifies the requirements for PC based announcement system and true colour
display boards; namely platform display boards, coach guidance display
boards, indoor video display boards and outdoor video display boards;
placed at various places of the stations with the feature of networking and
operation from a centralized place.
The True Colour Video -cum- Train Information Display System shall consist
of central controller with standby for redundancy, Central Data Switch,
Platform Data Controller, Video Display Controller, true colour display
boards of different sizes.
The true colour Indoor and Outdoor Video Displays shall display train
information, commercials, entertainment programs and other information for
passengers. The system shall allow programming the video information to
display from a remote place through WAN (Wide Area Network). It shall
capable of displaying video telecast from central place through WAN which
can be used at the time of emergency or on a special events.
6. GPS based Digital clock
Languages : Embedded C & Verilog HDL
Role : Involving in Hardware design, RTL coding,
and Documentations
Cross Platform: Nios9.0 & Nios 9.1 with Eclips environment
Tools & FPGA: Quartus2 9.1, nios9.1 modelsim for
simulation testing. The
FPGA used is
cyclone3
Description:
The Project involves the implementation of Digital clock which includes GPS
module, UART module and RTC module. The system involves various digital
clocks, like Master clock, Office clock and Platform clock. In these, the
system directly takes the UTC time from GPS and converts ITC as per RDSO
Specifications. The provided RTC is supplied with VBAT so that the time
will be same as the GPS. The time is synchronized directly from the GPS
receiver and this time is updated through all clocks by Master clock which
is built with battery also for back-up of time to maintain synchronization
along with GPS.This GPS Based Digital Clock is Approved by RDSO as per
standards.
7. PIS (Passenger Information System for INDIAN Railways)
Languages : Embedded C
Role : Involving in Hardware design, RTL coding,
and Documentations,peripherals testing
Cross Platform: Nios9.0 & Nios 9.1 with Eclips,Ride7
environment,coocox
Tools & FPGA: Quartus2 9.1, nios9.1 modelsim for
simulation testing. The
FPGA used is
cyclone3
Description:
The Project involves the implementation Passenger Information System for
AC, and NON-AC coaches. It provides Information about train location, next
halting station and late running status of train and alarm system will help
in enhancing passenger comfort especially during night hours. The GPS based
Passenger Information System is a cost effective solution to provide this
information to passengers on a moving train.
Personal Details:
Father Name : T. NARSIMULU
Date Of Birth : 20/07/1985
Hobbies : Reading Books of all categories, shopping
Permanent Address
Village : kowkuntla
Mandal : Chevella
District : RangaReddy
Pin : 501503
Address for Communication:
Praveen Kumar Tammali
Hyderabad
Mobile: 897-***-****
E-mail: **************@*****.***
Contact this candidate