VLSI, FPGA, Digital Design, Verilog, C, PERL, UVM

Niranjan Reddy

Mobile: +919********* Email : ******************@*****.***

Summary:

Over 18 months of experience in FPGA Validation.

Good at RTL design, simulation and synthesis using EDA tools.

Worked on multimillion gate SOC validation.

Experience in running pre-synthesis(RTL), post-synthesis simulations.

Experience working on ARM processors and assembly language coding.

Worked on industry standard bus protocols like AHB,AHBLite, APB etc.

Worked on industry standard on chip buses like PDMA etc.

Worked on development and validation of IEEE protocols like Ethernet(SGMII) etc.

Worked on validating peripherals like GPIO,PDMA,Timer,Watchdog etc.

Good knowledge on ASIC tools like Modelsim.

Fair knowledge on FPGA tools like Xilinx ISE, Libero.

Experience in working on Xilinx Virtex-6 FPGA’s.

Worked on validating Actel(Microsemi) FPGAs like Smart Fusion2 & Igloo2(65nm).

Worked on Automation of SmartFusion2 Security features using Perl Scripting.

Technical skill set:

HDL : Verilog, VHDL

HVL : System Verilog(Limited exposure), UVM

Programming Languages : ANSI C, C++, Micro-Controller Assembly Language

Operating systems : Linux, Windows

Other Protocols & Tools : Ethernet, AHB, APB

EDA tools exposure:

Simulation : Modelsim

Synthesis : Xilinx ISE,Synplify Pro

Silicon Validation tools : ActelLibero, Flash-Pro

FPGA : Xilinx V6, Actel SmartFusion2, Igloo2(not yet released)

Lab tools : Oscilloscope, Logic Analyzer,Ethernet MAC traffic

generator

Rational tools : Livelink, SVN, Bugzilla

Education:

Master of Technology in VLSI and Computer Engineering from IIIT-Hyd in 2013

Bachelor of Technology in Electronics & Communications from JNTU in 2011

Major projects implemented

1 Smartfusion2 FPGA Post silicon Validation, Microsemi, Hyderabad, India

Description

Smartfusion-2 is a G4 architecture FPGA with 5 million system gates of fabric. It

is based on ARM CortexM3 based sub-system. This project involves post silicon

validation activities for Smart fusion 2 product that is being launched by Microsemi in

the year 2013. As a team, we are responsible for validating all the features of micro

controller sub system and fabric logic.

Responsibilities

Technical

o Responsible for validating the APB peripherals which include Timer, Watchdog

& PDMA

o Responsible for validating Memory Sub-System block which has eNVMs built

into it.

o Involved in validating Ethernet (SGMII) block on silicon over Copper and Optical

Interfaces.

o Worked on developing application codes and fabric logic (RTL) for different use

cases.

o Worked on throughput analysis of various blocks in silicon

2 Igloo2 FPGA Post silicon Validation, Microsemi, Hyderabad, India

Description

Igloo2 is also a G4 architecture FPGA with 5 million system gates of fabric. It is

similar to Smartfusion2 but with the absence of ARM CortexM3 Processor. Here I used

CoreABC as the Master and wrote CoreABC Assembly Instructions to achieve My Goal.

Responsibilities

Technical

o Written CoreABC Assembly Codes for Memory to Memory Transfers.

o Responsible for validating the APB peripheral PDMA.

o Validated eNVM module by writing and reading back the written data and

printing it on Hyper Terminal or UART

o Validated different types of Security features.

3 Programming and Security Features Validation, Microsemi, Hyderabad, India

Description

There are Many Programming modes and Security related features present in G4

architecture which includes encryption protocols like AES128, SHA256 etc….

Responsibilities

Technical

o Responsible for Coming up with a way to test the Security features and Validating

them on silicon.

o Automated many Security features using Perl Scripting.

Course projects implemented

1. Project: “Design and Simulation of CDMA using VHDL”

Description: In this project the main concern is of designing and simulation of Seven

Channel CDMA Encoding and Decoding using HDL.

2. Project: “Simulation of a Digital FM Receiver in Software Defined Radio using VHDL”

Description: Simulated an FM Receiver that consists of Multiplier, Loop Filter, Numerically

Controlled Oscillator and FIR Filter using HDL.

3. Project: “Implementation of a Fast 32-bit Floating Point Multiplier Unit with Single

Precision in Verilog”

Description: Implemented a 32-bit Floating Point Multiplier with the Single Precision IEEE

754-2008 standard using Fast Adders, Booth Multipliers and achieved less PDP.

4. Project: “Implementation of Algorithm to Detect Open and Short Circuits on a VLSI

Layout in C”

Description: Given a post-layout net-list we report the open and short circuit faults in the

layout using data structures like skip lists and Graphs

5. Project: “Low Power and Area Efficient Multipliers with Minimum Leakage” using

Cadence Virtuoso tool

Description: In this Project we designed a new Full adder which is used in different

multipliers and obtained Less Area. Used different methods to reduce Leakage and Power.

6. Project: “Low Voltage, Low Power and High Gain CMOS Operational Trans-

conductance Amplifier” using Cadence Virtuoso tool.

Description: In this Project we used an active positive Feedback with feed -forwad technique

and frequency dependent current Mirrors and achieved the above.

Strengths & Expertise

Achievement Oriented with Good people management skills and ability

to manage change with ease.

Proven strength in problem solving and analysis

Good Communication, interpersonal, learning and organizing skills matched

with the ability to manage stress, time and people effectively.

Contact this candidate