Project Design

R ES UM E

Antyakula Ramesh Email : ******.*****.****@*****.***

**,******,**** ******* *******, ************@*****.***

Kalyan nagar, Bangalore- 560043. Phone No : 098********, 089********

OBJECTIVE:

To utilize and enhance the knowledge and skills in the field of Digital and Analog VLSI CircuitDesign,

ASIC/FPGA Hardware Software Co-Design and Computer Architecture.

WORK EXPERIENCE:

A s a part of my Mtech thesis work, I am Working in NVIDIA as a 8 months intern till august

31,2014.I am in a CAD-DFT team.

My work at Nvidia :

1. I was Creating regressions for various checks for validating DFT flow with good coverage and

storing the generated report in the golden directory for future reference .The Checks include :

Multiple driver check, Tri state buffer check, validation of DFT in scan mode, validation of DFT

in scan in by_pass mode, validation of DFT in scan compression mode, validation of DFT in scan

compression with by_pass mode, chain extraction in partition, Grouped scan blocks check,

Pipeline blocks check, chain extraction of partition with compressed mode,scan violation etc.

Created around 60-70 regressions covering different aspects of DFT .

2. Running checks on chips(CPU’s, GPU’s) at various modes and verifying that run is clean, no

differences.

3. Debugging C++ and TCL programs.

4. Writing TCL scripts, xml and yaml scripts to assist in the enhancement of EDA tools.

5. Presently working in a IEEE1500 test standard Design,writing tcl scripts,creating regression to

support the devolpment of the design. These regressions include different clock evaluation based

on context, wrapper boundary register insertion, scan requirement,scan violation check etc.

6. Validating I1500 flow in various chips(CPU’s and GPU’s).

EDUCATIONAL QUALIFICATION :

MTECH : Pursuing Mtech from IIIT H yderabad in VLSI and computer engineering 2012-2014 batch,

secured a CGPA of 7.8 .

BE : Completed BE from Swami vivekanand technical university in year 2011,Bhilai.Secured 74.5%.

SSC : Completed from CGBSE board with 72% in year 2005.

HSC : Completed from CGBSE board with 77.5% in year 2003.

COMPUTER/TECHNICAL SKILLS :

S/W Languages: C, C++ basics, python Script, perl, tcl, data structures,Algorithms..

H/W Languages: verilog, vhdl, SV(basics).

Operating Systems: windows, linux.

EDA tools : modelsim,cadence(Virtuoso schematic Editor, Virtuoso layout Editor,Analog Design

Environment,Assura),tanner,LTspice,Quartus,xilinx,Icarus.

DFT tools: DFTAdvisor, FastScan, TestKompress, Etchecker .

COLLEGE PROJECTS :

PROJECT 1: Design of “snoopy based write invalidate cache coherency protocol” using

verilog(working).

Description : Snooping Protocols maintain coherence for multiple processors.To maintain the

coherence requirement in snooping protocols, write invalidate protocol is used.Language used is

Verilog,page replacement policy used is least recently used(LRU).Designed 7 blocks (cache A,cache

B,CPU A,CPU B,memory mapping unit,memor y bus controller and memory) to accomplish this cache

protocol fully functional.Caches are designed using 2-way set associative.

PROJECT 2: Design of a “fully differential folded cascade opamp”.

Description :Tool used for design is Cadence virtuoso with 180nm tehnology.Traddeoff among factors

as bandwidth,gain & phase margin,bias current,output swing,slewrate,and power are made evident.A

Gain Margin of 77 dB,phase margin of 65 Deg,swing of 3.2V,slewrate 150uv/s,PSRR of 106dB,CMRR

of 104dB,settling time of 22ns and power dissipation 625uW were achieved.It find its appliaction in

ADC,DAC,Switced capacitance filters etc.

PROJECT 3: Design and analysis of “Energy recovery logic circuits (Adiabatic circuits)”.

Description :Tool used for design is Cadence virtuoso with 180nm tehnology.Compared the

performance of different adiabatic logic circuits (ECRL,PFAL,2PASCL, Pass transistor logic) with

traditional CMOS using 16-bit carry lookahead adder.It shows that designs based on adiabatic principle

gives superior performance when compared to traditional approaches in terms of power even though

their transistor count is high.Power dissipation of (ECRL,2PASCL,PTL,CMOS) is found to be

143.4uW,51.7uW,175uW,256uW respectively.And transistor count is 1656,2252,888,1592 respectively.

The results are ploted and delays,PDP are made shown.La yout was also carried out.

PROJECT 4:Design of high frequenc y clock generator “Digital lock loop(DLL)” in Cadence Virtuoso.

Description :Tehnology used is 180nm.A frequency of 3Ghz,jitter of 12 ps,locking range of 17ns is

achieved.Problems like charge sharing and false locking phenomenon were taken care.The simulation is

performed for slow, t ypical, and fast process corners for temperatures between 0 and 70 DegC and

supply voltage tolerance of 10%.Its applications are in clock -generator,synthesizer,multiplier,data

recovery, in local oscillators etc.

PROJECT 5: Design of “UART protocol” .

Description :Design uses VERILOG as design language to achieve the modules of UART. Using

XILINX software,Altera DE1 board FPGA to complete simulation and test.On the PC side, Window's

HyperTerminal program is used as a virtual terminal to interact with the board. To be compatible with

our customized UART, it has configured as 9600 baud,1 start bit, 8 data bits, 1 stop bit, and 1 parity

bit.The results are stable and reliable data transmission with great flexibility, high integration.UARTs

are frequentl y used in conjunction with the EIA (Electronic Industries Alliance) RS-232 standard, which

specifies the electrical, mechanical,functional, and procedural characteristics of two data communication

equipment

PROJECT 6 :Project on python based “DX ball game” .

Description : Paddle and Ball Game to break the series of bricks without letting the ball to touch the

ground, implemented till 3 stages with different difficulty levels with 3 lifes,points were given for each

brick break,some bricks have some extra powers. Implemented using pygame an open source platform.

PROFESSSIONAL QUALIFICATION:

Knowledge about Advance computer architecture, shell script,Digital circuit design,advance

vlsi design, vlsi architectures.

VHDL,Verilog HDL languages, Programming in 8085.

Knowledge about Operating systems,Analog mixed signal.

DFT: Familiar with scan-insertion, pattern generation, pattern compression, mbist, lbist, jtag tap

controller,memory repair.

EXTRA CURRICULAR ACTIVITIES:

Active member of Blood Donation Group,Donate Blood-Save life, LETS-VOTE campign.

Activie member of an N.G.O. named Friends For Seva .

Class Representative in Bachelor of Engineering for 4 years.

Getting scholarship for Masters,Securing a rank of 4500 in all India Graduate test(GATE) out of

1,80,000 aspirants.

Been a captain of our college cricket team,Participated in skits and dance at various occassions.

DECLARATION:

I hereb y declare that,the information provided is true to the best of my knowledge.

Place: Bangalore. (A.Ramesh)

Contact this candidate