VHDL,Verilog,FPGA,ASIC

Alok Kumar Chaudhary

Mobile: 91+971******* Email : *******@*****.***

Objective

To work as a Digital hardware designer in VLSI that challenges and enhances my technical skills and offers future growth and learning opportunities.

Education

Year Degree/Exam Institute GPA/MARKS

2014 Electronic & Communication SMVDU, Jammu 6.36

2009 CBSE,Class XII Kamal Model School, New Delhi 78%

2007 CBSE,Class X Kamal Model School, New Delhi 77%

Paper Publication

Alok Kumar Chaudhary,Pranay Prathik, Swastik Gupta and Vipin Kakkar, ”Improved Digital Design of BPSK Modulator Using Look –up Table ” has been presented at the Second International Conference on Advances in Computing, Communications and Informatics (ICACCI-2013) conducted by IEEE held at MYSORE,INDIA.

Gauri Shankar Thakur, Deepak Mishra, Anubhav Jain and Alok Kumar Chaudhary ”A Fail-Safe

Communication Method For Vechicular Accidents ” has been presented at the 5th International Academic Conference on Electrical, Electronics and Computer Engineering (IACEECE) held at Hyderabad on 22ndSeptember 2013.

Projects

CMOS based Thermoelectric Power

Generator - ( Sept’13 – may’14) : As my senior year B. Tech. project under the guidance of Dr. Vipin Kakkar,

This project at the design, modeling, fabrication, and characterization of CMOS Microelectromechanicalsystem –

based the thermoelectric power generators (TPGs) to convert waste heat into a few microwatts of electrical

power.The thermal source will be body heat and will act like power supply to Medical Implant inside the body like

Pace Maker. Tool required :- Silivaco (Deckbuild)

Design and Verification of Time to Digital converter - (may‘13–july ‘13): This project was a part of my summer internship at VNIT, NAGPUR under the

guidance of Dr. R.B.Deshmukh . My work included design and verification of High resolution Time to Digital Converter that alow to measure the time delay between two signal with high resolution and provided digital representation of time . IOPAD are also used in this design . The design is implemented by UMC 180 nm CMOS Technology in ASIC DEISGN FLOW. Tool required :- Simulated by Modelsim6.2b,Logic synthesis by Design Complier(Synopsys), Layout by Encounter(Cadence).

Improved Digital Design of BPSK Modulator Using Look – up Table - (Feb’13–April ‘13 ): I have

proposed a new & Improved architecture of the BPSK modulator with optimized resource utilization. In this design,I have used single sine wave generator using LUTs technique to generate both sinusoidal carrier signal(sine wave with 0 degree and 180 degree phase shift). The architecture of modulator is implemented using VHDL language. This project was guided by Assoc. Prof. Dr. Vipin Kakkar, SMVDU. Tool required :- Simulated by Modelsim6.2b, Synthesized by Xilinx 9.2i, Implemented in Spartan3E

Study of Process variation effects on 6T SRAM cell in sub-threshold region - (Dec’12-Jan’13):This project was done during my winter internship at ABV-IIITM,Gwalior,under the guidance of Assoc. Prof. Dr.Manisha pattanaik . I have analysed the intra and inter die variation during process variation which are the cause of large no. of failure in a SRAM array degrading the design yield. I also focuses on low area Adaptive body bias technique to compensate the failure to improve the SRAM reliability in sub-threshold region and yield using IC cad Tool (Silvaco). Tool required :- Silivaco (Gateway).

Design of 8 Bit Microprocessor Using VHDL - (Sep’12- Nov’12) : In this project,I designed an eight bit microprocessor which closely resembled the functionality of an 8085 microprocessor. It consists of datapath and control unit. Datapath can perform numerous algorithms on the basis of control unit designed. This project was guided by Assit. Prof. Mr. Anil Bardwaj (SMVDU) . Tool required :- Simulated by Modelsim6.2b,Synthesized by Xilinx 9.2i, Implemented in Spartan3E.

Technical Skill

Language : C, VHDL, Verilog, MATLAB, Assembly Language, Basic of TCL Scripts.

EDA Tools : Xilinx ISE, Modelsim, Synopsys -(Design Compiler,Formality), Cadence-(NC–

Verilog,

SOC Encounter, Cadence Virtuoso), Silvaco –( Gateway,Deckbuild & DevEdit).

Operating System : Linux, Windows 95/98/2000/XP/2007/2008.

Summer and Winter internship

• SUMMER INTERNSHIP (May’27 2013-july’16 2013): “ Design and Verification of Time to Digital

converter”. The design is implemented by UMC 180 nm CMOS technology in ASIC DESIGN FLOW

at VNIT Nagpur under Prof. Dr. R.B.Deshmukh.

• WINTER INTERNSHIP (Dec’12 2012 -Jan’13 2103): “A study of process variation on 6T SRAM

cell in sub-threshold” at ABV-IIIT Gwalior under Assoc. Prof. Dr. Manisha Pattanaik.

• SUMMER TRAINING (June’12 2012-July’12 2012): “Synthesis and Verification of Digital system

on FPGA and CPLD” at CETPA InfoTech Noida.

Achievements

• Won the best performance award in summer training course on VLSI by CETPA Infotech Noida.

• Won 1st prize in various events of Titiksha (technical fest) and Resurgence (cultural fest) 2011 at

SMVDU University.

• I was a member of “KABBADI TEAM” in our school and college, where i secured 1st place.

• Working in a group of four, our project was selected amongst the top 20 projects out of the 117 projects

received worldwide for the “IBM/IEEE Smarter Planet Challenge 2012”

Personal Information

Father Name : Mr. Prabhat Kumar Chaudhary.

: 15th January 1993.

Date of Birth

Known Languages : English and Hindi.

Present address : Flat no. 716, pocket-1, phase-2, sec-14, Dwarka, New Delhi -110075, India

Permanent address : Flat no. 716, pocket-1, phase-2, sec-14, Dwarka, New Delhi -110075, India.

DECLARATION

I hereby declare that the information furnished above is true to the best of my knowledge.

Alok Kr. Chaudhary

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