VELLORE INSTITUTE OF TECHNOLOGY

VELLORE,TAMILNADU

INDIA

Mr. AJIT SHRIDHAR GANGAD

E-mail: ace3a1@r.postjobfree.com

Mobile No: +91-779*******/814-***-****

Objective:

To grab an opportunity and set myself a goal where I can be in novative and attain a

challenging position by exercising my interpersonal and professional skills to the fullest

for the growth of the organization and mine as well.

Academic Qualifications:

Degree/ Year of Percentage

Board/University School/Institute

Examination passing / CGPA

8.3 CGPA

M.Tech- Vellore Institute of Vellore Institute of

May-2015 (First Class

1st year Technology(VIT) Technology(VIT),

(Pursuing) with

(VLSI Design) University,Vellore.(TN) Vellore.(TN)

Distinction)

B.E Vidya Pratisthans 64.93%

(Electronics and Pune board College of Engg. May-2012 (First Class)

Telecom.) Baramati.(MS)

79.33%

New Arts Commerce

(First Class

H.S.C Pune board and Science College Feb-2008

with

Ahmednagar.(MS)

Distinction)

80.40%

New English School (First Class

S.S.C Pune board Mar-2006

Parner.(MS) with

Distinction)

Software Skills:

Software Languages : C, PERL, TCL,Embedded C

Hardware Languages : Verilog HDL

Operating System : Windows, Linux

VLSI CAD Tools:

Altera Tool :Quartus-II

Mentor Graphics Tools : Modelsim

Cadence Tools : NCLaunch, RTL compiler, SoC Encounter, Virtuoso, Assura.

Areas of Interests:

Digital system design

ASIC Design

CMOS VLSI Design

Modeling and Simulation of Nanoscale Devices-FinFET

FPGA Based system Design

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Academic Projects:

[1] Title of the Project : Design of 1-bit Full Adder by using FinFET at 30nm

Technology.

Team size : Three members

Project Role : Architecture and Circuit Design.

: 20th July 2013 -15th Dec, 2013.

Duration

Software :Cadence Virtuoso

About the Project:

FinFET is a replacement to MOSFET. Because of having more static power dissipation while

scaling MOSFET we have to go for another transistor (FinFET).We have designed power

efficient 1-bit adder using FinFET with the help of Cadence virtuoso.

[2] Title of the Project : Low Power SRAM Design using Independent Gate

FinFET at 30nm Technology.

Team size : Three members

Project Role : Architecture and Circuit Design.

: 20th Jan 2014 -15th May, 2014.

Duration

Software : Cadence Virtuoso

About the Project:

We have designed SRAM cell using double gate FinFET. The low power in SRAM is achieved

by driving the two gates of FinFET independently. We have designed some SRAM circuits

using FinFET and compared their results. After that, using the best configuration we have

designed 8x8 memory array.

[3] Title of the Project: Vehicle Tracking System using GPS and GSM module

with ARM controller

Team size : Three members

Project Role : Coding and Hardware Design

20th Dec 2011 -15th Mar,2012.

Duration :

Software and language : Keil and embedded C

About the Project:

This project involves tracking the vehicle using GPS module means it captures co-

ordinates (latitude and longitude) and sends it to the LPC2148 controll er serially.

Controller captures ADC’s data from milk vehicle along with GPS co-ordinates and send

it through GSM module to the server. At server side location of vehicle is shown on

Google map.

[4] Title of the Project: Implementation of RISC Stored Program Machine by

Verilog HDL

Team size : Three members

Project Role : Architecture Design and programming.

: 20th Jan 2014 -15th May, 2014.

Duration

Software and language : Cadence NLaunch and Verilog

About the Project:

In this project, we have designed the machine which consists of three functional units: a

processor, a controller and memory. Program instructions and data are stored in

memory. Instructions will be fetched synchronously from memory, decoded & executed.

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[5] Title of the Project: Implementation of UART by Verilog HDL

Team size : Three members

Project Role : Architecture Design and programming

: 20th Jan 2014 -15th May, 2014.

Duration

Software and language : Cadence NCLaunch, RTL compiler, Soc Encounter and Verilog

About the Project:

In this paper, we have implemented a UART(Universal Asynchronous Receiver

Transmitter) design implemented using Verilog HDL. The functionality is verified by

transmitting the data from the transmitter module and receiving the same data in

receiver module.

Strong Points in Myself:

Committed and determined person towards the achieving the Goal.

Intellectual thinking.

Flexibility in technical area.

Academic achievements, Publications and Extra-Curricular Activities:

“Design of 1-bit Full Adder by using FinFET ” Paper has published in

International Journal of Applied Engineering Research (IJAER) .

EC-GATE-2013(Graduate Aptitude Test in Engineering) is qualified with

498 GATE score.

Worked on Microcontroller projects based on 8051, AVR, ARM (LPC2148).

Robotics: Worked on Wireless Robotics projects(based of RF module) &

participated in Roborace, Robowar competitions.

Attended workshop on “VLSI system verification using system Verilog ” at

VLSI Design,SENSE,VIT University, Vellore

Active member of National Service Scheme(N.S.S)

Personal Profile :

Name : AJIT SHRIDHAR GANGAD.

Father’s name : SHRIDHAR VITHOBA GANGAD.

Date of Birth : 24, Sep, 1990

Gender : Male

Marital Status : Single

Languages Known : English, Hindi and Marathi

Address : At Post-Karandi, Tal-parner, Dist-Ahmednagar,

State-Maharashtra,Pin:414303

Declaration:

I hereby declare that the above written particulars are true to the best of my knowledge

and brief.

Date: 10, July, 2014

Place: Vellore. AJIT SHRIDHAR GANGAD.

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