Project Design

RESUME

P. Ram Kumar.

Mobile: +91-973*******

Email: **********.***@*****.***

To seek a challenging career and prove my excellence in that field by

contributing my best to the development of the organization.

Class/Course Board of Study Marks

Name of the Institution Year of

Passing

SBK HSS, Tamilnadu 2009

XII Aruppukottai. State Board 72

SBK HSS, Tamilnadu 2007

X Aruppukottai. State Board 77

Design Automation Languages & Scripting & VLSI Design/Process

Tools Knowledge

PLC Verilog CMOS

SCADA System Verilog FPGA

DCS C & C++ Digital Design

Perl Verification

Cadence Virtuoso Synthesis

NC Sim DFT

RTL compiler Layout

Encounter Physical Design

STA

> Indian Institute Of VLSI Design & Training - Bangalore, Karnataka

Post Graduate Diploma in VLSI Design & Technology

Six Month Full Time Course in VLSI Design based on Cadence flow.

> Completed " Post Graduate Diploma In Industrial Automation at "

Prolific System & Technology Pvt Ltd Chennai.

PROJECT : Major Project - B.Tech Electrical & Electronics Engineering

Organization : Lucas TVS, Chennai.

Title : Car Alternator Testing Using Labview

Tools : Labview 2009

Duration : 6 month

Team Size : 3 members

Description : Our Goal is to Increase the performance of the Alternator

by testing it using Labview. In this we checked the major parameters like

Voltage, Speed & Power with the reference Value. By doing this we are

increasing the reliability of the testing & efficiency of the Alternator

thereby production is increased.

PROJECT: Verilog Project - Post Graduate Diploma in Vlsi

Title : Design of Synchronous FIFO

Tools : NcSim, Simvision

Language : HDL -Verilog.

Team Size : Individual.

Description: A FIFO is a circuit which gives output in the form of First in

First Out i.e. the data which comes first at input is the first one that

goes out. Coding of FIFO was done by using Verilog language and after that

Test Bench coding was done in Verilog and then inputs were given in the

Test Bench and output waveform was checked using simvision.

Role & Responsibility:

> Development of Verilog Code.

> Development of Test bench.

> Test cases to verify the functionality of the DUT.

PROJECT: System verilog Project - Post Graduate Diploma in Vlsi

Title : Design of APB Slave.

Tools : NcSim, Simvision

Language : HDL -Verilog, System Verilog.

Team Size : Individual.

Description: An APB Slave is used for communicating low frequency bus used

in SOC architecture. Coding of APB was done by using Verilog language and

after that Test Bench coding was done in System Verilog using one of the

test methodology then inputs were given in the Test Bench and output was

checked using simvision.

Role & Responsibility:

> Development of Verilog Code.

> Development of System Verilog test bench environment.

> Test cases to verify the functionality of the DUT.

PROJECT: FPGA Project - Post Graduate Diploma in Vlsi

Title : Design of Stop Watch.

Tools : NcSim, Simvision, Xilinx FPGA.

Language : HDL -Verilog.

Team Size : Individual.

Description: In this project a Stop Watch was designed using Verilog

language. The Stop watch coded here will be able to keep time till 10 min.

It will be a 4 digit stopwatch counting from 0:00:0 till 9:59:9. The Stop

Watch will be in the format M:SS:D.

Role & Responsibility:

> Development of Verilog Code.

> Development of Test bench.

> Test cases to verify the functionality of the DUT.

> To Synthesize the Design and to generate the bitmap file for FPGA.

PROJECT: Analog Design & Layout Project - Post Graduate Diploma in Vlsi .

Title : Design of PLL.

Tools : Cadence virtuoso

Team Size : Individual.

Description: To draw schematic and Layout for the PLL.

Role & Responsibility:

> Draw the schematic for the design.

> To verify the characteristics of the design by using test schematic.

> To draw the layout for the design.

> To check the DRC, ERC & LVS errors.

PROJECT: Physical Design Project - Post Graduate Diploma in Vlsi

Title : Physical Design & Verification of DTMF CHIP.

Tools : Soc Encounter, RTL Compiler.

Gate count / Area : 6K

No of clock : 2

Macro count : 4

Utilization : 70.1%

Technology/ Layers : TSMC 0.18 micron / 6 Metal layers

Team Size : Individual.

Objective : To do the synthesis, floor planning, Power planning, placement,

CTS, Routing, Design signoff, Generating GDS II.

Role & Responsibility:

> Synthesising RTL code

> Placement for the Macro.

> Power planning to reduce IR Drop.

> Detail Routing & Timing analysis.

> To fix the DRC Violations using search & Repair.

PROJECT: Physical Design Project - Post Graduate Diploma in Vlsi

Title : Physical Design & Verification of Fir Filter.

Tools : Soc Encounter, RTL Compiler.

No of clock : 1

Macro count : 0

Utilization : 70.1%

Technology/ Layers : TSMC 0.18 micron / 6 Metal layers

Team Size : Individual.

Objective : To do the Synthesis, floor planning, Power planning, placement,

CTS, Routing, Design signoff, Generating GDS II.

Role & Responsibility:

> Synthesising RTL Code

> Power planning to reduce IR Drop.

> Detail Routing & Timing analysis.

> To fix the DRC Violations using search & Repair.

Name of the Area of Exposure

Industry

Focus Tech Media Embedded Technology

NCCT Technologies Embedded

Technology

> Attended 5 days' Workshop on Basic of Electronics conducted by

Electronics For You held in our University on 13th Dec and 17th Dec

2010.

> Attended 2days Workshop on Recent Trends in Embedded and Intelligent

Systems held in Ramakrishna College of Engineering-Coimbatore on 24th

and 25th Sep 2010.

> Member in ISTE and IE.

> A member in "Photographic Club", KLU from 2011-2013.

> Active participant in National Service Scheme.

DATE OF BIRTH : 07.11.1991.

GENDER : Male.

FATHER'S NAME : V.Padmanaban

MOTHER TONGUE : Tamil

LANGUAGES KNOWN : Tamil, English, and Telugu.

NATIONALITY & RELIGION : Indian & Hindu

PERMANENT ADDRESS : No 24 Ambalam Sammy Naicker Street.

Periyapuliyampatti, Aruppukottai.

Virudhunagar District.

DECLARATION:

I declare that the above information's

furnished by me is true and best of my knowledge. If given a chance to me

in your concern I will do my best.

Place: Bangalore

P.Ramkumar

Date: 22/05/2014

Signature [pic]

Professional Objectives

Academic Records

Skills Summary

TECHNICAL PROFICIENCY

ACADEMIC PROJECT

INPLANT TRAINING

CO-CURRICULAR ACTIVITIES

EXTRA-CURRICULAR ACTIVITIES

PERSONAL DETAILS

Contact this candidate