Design Engineer
Resume:
Yue Yang
Thornhill, Ontario, L3T 0C8
Phone: 1-647-***-****
E-mail: *********@*****.***
Qualifications:
Extensive experience in both analog and digital design
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7+ years of mixed signal design experience
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Successfully lead ASIC design from concept to production
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Experience with FPGA, PCB, RTL, package, transistor level design
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Major contributor in many silicon proven tapeouts
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Strong Team Player, Excellent communications skills
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Strong motivation to excel
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Education:
Bachelor of Electrical Engineering University of Toronto 2003 – 2008
Master of Electrical Engineering University of Toronto 2008 – 2010
Patent:
Yue Yang, Afshin Rezayee, 2011, APPARATUS AND METHOD FOR DETECTING RFID
SIGNALS, USA, Patent. NO.: US8,472,560 B2, June 25, 2013
Skills:
Verilog, Verilog-A, SPICE, MATLAB, C, Perl, Cadence Spectre, Cadence AMS, Calibre,
Cadence Allegro, Altera FPGA, Microsoft Office
Work Experience:
ASIC Design Lead Kili Technologies Corp. July 2010 – Present
• Coordinate overall ASIC design schedule, heavily involved in design efforts
o Secure SoC for mobile Point of Sale (POS) terminal
o Design is in 90nm CMOS TSMC
• Lead NFC (Near Field Communication) analog frontend design
• Lead final chip integration and sign off
• Work with designers to acquire major design IPs
o MCU (EnSilica), SRAM, eFlash, eFuse
• Lead chip characterization effort
o Package design
o Evaluation board PCB design
o Circuit characterization
o Reliability tests
Design firmware routines execute mixed signal related algorithms
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o Calibration, field detection, temperature and voltage monitor
Lead the effort to bring silicon proven ASIC design to production
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Major contributor to Kili proprietary mobile POS terminal PCB design
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Digital Designer Snowbush IP, Gennum Corp. April, 2008 – June, 2010
Led USB 3.0 PHY digital control design
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o Team members are in Taiwan, India, and USA
Led digital design for various projects on SATA PHY, PCIe PHY, and USB PHY
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Co-designed digital control for PCIe 3.0 PHY
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o Implemented Decision Feedback Equalizer adaptation algorithm
o Implemented calibration control for critical analog components such as CDR,
VCO, and high speed comparators
Designed models for high speed analog circuits to speed up simulation time
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Participated in designs for various wireline communication protocols
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o SATA, PCIe, 10G KR, XAUI, GPON
o Bit rate up to 16Gbps for upcoming protocols
Set up AMS simulation flow to verify mixed signal control loop
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o Combination of RTL, Verilog-A, SPICE
Worked on 90nm, 65nm, 45nm
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Application Engineer/Digital Designer Snowbush Inc. May, 2006 – Aug, 2007
Setup demonstration platform
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Performed product demonstrations to customers
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Helped customers to setup characterization stations to characterize test chips
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Characterize high speed serial-deserializers
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o Bit rate ranges from 3Gbps to 10Gbps
o SATA, PCIe, 10G KR, XAUI, GPON
Run digital verification suite and fix design issues
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Personal Interests:
Soccer, Basketball, Volleyball
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Strategy board games
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Contact this candidate