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Verilog Hdl,Virtex 5 Fpga,Xilinx Ise 13.2,Amba(Axi,Ahb,Apb)

Location:
Hyderabad, AP, India
Posted:
May 01, 2014

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Resume:

CURRICULAM VITAE

Y.SUDHEER KUMAR

H.No:*-**/**/1/1

8th battalion A.P.S.P.ROAD E-mail:acdx0k@r.postjobfree.com

Kondapur, Hyderabad Mobile: 917-***-****

CARRER OBJECTIVE:

To join in good reputed company/platform, which helps to turn my theoretical knowledge

into practical .At the same time to increase my skills which help in company’s growth.

TECHNICAL SKILLS:

Verilog HDL

Worked on Virtex 5 FPGA

Worked on Xilinx ISE 13.2 design, EDK & SDK

AMBA Protocol (AXI, AHB, APB)

Worked on Logic analyzer

Course School/College University/Board Pass out Result

ME OU 2013 74%

Osmania University

(Digital Systems)

RRS College of Engineering

B.Tech

JNTU-H 2011 74.58%

(ECE) & Technology

Intermediate

(

M International Junior College BIEAP 2007 89.10%

P

C

)

Sri Rama High School 2005 79.67%

SSC BSEAP

EDUCTIONAL QUALIFICATION:

LIST OF PUBLICATIONS:

[1] Sudheer Kumar Yezerla and B.Rajendra Naik, “Design and estimation of delay, power and

area for parallel prefix adders”, An International Conference on Recent Advances in Engineering

and Computational Sciences (RAECS 2014).

PROJECTS UNDERTAKEN:

1. DESIGN OF ADVANCED MINIATURE PARALLEL PREFIX ADDER USING FPGA’S

(ME PROJECT):

To design the brent kung adder (one type of a parallel prefix adder), which has

better power delay performance and occupies less area than the basic sequential

adders(ripple carry adder, carry skip adder, carry select adder) and other parallel adders

like kogge stone adder, sparse kogge stone etc.,These adders are designed in verilog HDL

in Xilinx 13.2 ISE and compared the characteristics of adders like delay, power, area etc.,

and done FPGA for all the adders using Xilinx virtex 5 FPGA and observed the delay for

all the adders using logic analyzer.

2. FPGA BRIDGE BETWEEN INTERNAL AND EXTERNAL NETWORKS:

To implement the bridges between FPGA’s by using Aurora protocol (which is a

point to point serial link) internally and TCP/IP externally for efficient full duplex

communication (file sharing).The design is implemented using Xilinx ISE tools

(EDK,SDK, logic core generator), wire shark(packet protocol analyzer).

3. LOW POWER H.264 VIDEO COMPRESSION ARCHITECTURES FOR MOBILE

COMMUNICATION :

Video compression plays an important role in today’s wireless communications. It

allows raw data to be compressed before it is sent through a wireless channel. However,

video compression is computation-intensive and dissipates a significant amount of power.

This is a major limitation in today’s portable devices. Existing multimedia devices can

only play video applications for a few hours before the battery is depleted. The latest

video compression standard MPEG-4 AVC/H.264 gives 50% improvement in

compression efficiency compared to previous standard.

4. INVESTIGATIVE WIRELESS ROBOT (BE PROJECT):

To design and implement an Investigative wireless robot for the applications

where human cannot go. The main aim is to investigate narrow passages such as checking

underground water piping or sewage piping for any blockage etc.

EXTRA CURRICULAR ACTIVITIES:

Organizer of a two day national level workshop on “HETEROGENEOUS

COMPUTING” organized by Dept. of ECE, CSE and AMD (INDIA).

Attended a workshop conducted by XILINX on VERILOG for 4 weeks and have a good

knowledge on Xilinx virtex5 kit.

Participated in open book competition conducted by IEEE student branch.

Participated in Non-technical programs like painting, quiz, treasure hunt etc.,

ACHIEVEMENTS:

Topper of the school in 10th standard and received an award by educational minister in

2005.

Participated and won several awards in various social and cultural programs in school

and college level competitions.

HOBBIES:

Gardening

Cooking.

Listening music

PERSONAL PROFILE:

Name : Y.SUDHEER KUMAR

Father’s Name : Y.SUNDARAM

Sex : Male

Marital status : Single

H.No: 2-41/16/1/1,8th battalion APSP road,

Permanent Address :

Kondapur, Hyderabad.

DECLARATION:

I hereby declare that all the information provided above is true and the best of my

knowledge and belief.

Place:

Date: (Y.SUDHEER KUMAR)



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