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Project Design

Hyderabad, AP, India
April 29, 2014

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Srikanth Bitra

Contact Flat No:***, Voice: +91-991**-*****

Information Anandh bhavan, Fax: NA

Srinagar colony main road, E-mail:srikanth

Hyderabad 500073

Career Looking for a responsible position in a VLSI company with a view to utilize

Objective and enhance my skills and experience towards professional growth.

Research 1. VLSI Arithmetic


2. Quantum Computation

Education 1. Bachelor of Technology, (Electronics and Communication Engi-


Vardhaman College of Engineering, Jawaharlal Nehru Technological

University (JNTU-H), Hyd, 2014(Expected) 73.3%

2. +2,Intermediate Public Examination, Hyd, India, 2010 86.7%

3. Secondary School Certicate, Hyderabad, India, 2008 85%

Certifications Cadence VLSI Certication Program-2013 (CVCP), certified by Cadence Design

Systems Inc, Bangalore

Honours and 1. Merit Certificate in ”BRAIN STROM” at INNO’E’VENT’13 held by

Awards PRRM college

2. Event Organiser for SATELLITE HOUSE - TECHNOLITES’12 at VCE.

3. Member, National Service Scheme(NSS)

Projects 1. Designing of Partial Tree Multiplier using Verilog HDL

No. of Members: 2

Tools: 1. NC - Verilog Simulator

2. Code Coverage

3. RTL - Compiler

Project Description: The partial tree multiplier is an efficient high

speed multiplier which is a tradeoff (speed and size)between a normal

binary multiplier and a full tree multiplier.Here, k*k multiplication

is performed by passes through the CSA tree where ’h’ is less than

’k’. The partial tree multiplier is also known as High Radix mul-

tiplier where the differernce is quantitative rather than qualitative.If

the number of operands are significantly small we tend to view as high

radix and if the operands are fraction of K ie k/2 or k/4 it is viewd as

partial tree multiplier.The design consists of (h+2) bit input CSA tree

for adding the cumulative partial products and stored in carry save

form in sum and carry registers,which are fed back in CSA tree with

next cycle of operands.At the end of each cycle h-bits are shifted in to

the h-bit adder producing the lower cumulative partial product.The

sum and carry registers are propagated at the end of multiplication

cycle to get upper half of partial product .

2. Advanced Peripheral Bus based Universal Asynchronous Re-

ceiver Transmitter interface for SoC

No. of Members: 4

Tools : 1. NC - Verilog Simulator

2. Code Coverage

3. RTL - Compiler

Project Description :The APB based UART is a slave interface for

UART (full duplex ) communication system, consists of

1)APB interface

2)Baud rate generator

3)TX block

4)RX block

The APB interfece block is used to interfece with the APB bus struc-

ture with the slave.The baud value generated from APB interfece block

is fed to baud rate generator for generating TXCLK and RXCLK sig-

nals given to Tx and Rx blocks.The Tx block transmits the data from

registers loaded with PWDATA serially whereas the Rx block receives

the data serially and is read into PRDATA.write and read operations

cannot be performed simultaneously.

3. Full custom design of BCD to Decimal Decoder

No. of Member: 2

Tools: (Virtuoso) 1. Schematic Editor

2. Spectre

3. Layout Editor

Project Description: Decoder designed to accept four BCD inputs

and provide ten mutually exclusive LOW outputs.when all the input

bits ie BCD bits are greater then nine, then all the output bits are

active HIGH.The design is verified using ADE tool and layout is im-

plemented with no DRC and LVS errors.

4. Conversion of IEEE 754 Floating Point to Binary

No. of Member: 5

Tools: 1. NC - Verilog SimulatorSpectre

2. Code Coverage

Project Description: IEEE 754 is a single precision (32- bit) repre-

sentation of a floating point number. It is represented by




Here the mantissa is normalised.The representation of SEM is under-

stood, the verilog code implemented and simulation is performed.

Computer 1. Hardware Description Language: Verilog


2. Programming Languages : C, C++, JAVA

3. Operating Systems : Windows, Linux

4. Scripting Languages : Tcl, PERL

5. Tools : 1. Matlab 2. Multisim

3. Virtuoso ADE 4. NC-Verilog Simulator

5. Spectre 6. Code Coverage

7. SOC Encounter 8. Encounter RTL Compiler

Personal Name : Srikanth Bitra

Details Mother’s Name : B. Devi

Father’s Name : B. Shiva Prasad

Date of Birth : 11-Feb-1993

Languages Known : English, Hindi, Telugu

Hobbies and Interests : Listening to music, Football

Srikanth Bitra

Contact this candidate