Patel Chiragkumar Mo.No. +919*********
To work in a competitive environment that effectively utilizes my analytical, interpersonal,
leadership and organizational skills to conceive and achieve solutions. I am willing to pursue a
career in VLSI, where opportunity exists for innovation, knowledge enhancement and to utilize
the skill to the best of my organization that I serve.
Training experience in VLSI & Communication Domain.
Exposure in ASIC/DFT/Chip Validation/Soc Verification
Strong analytical skill, Problem solving technique
Language exposure in C, C++, System Verilog, Verilog,VHDL,Pearl scripting
Working in Live Project undertaken by Vector India Pvt Ltd.
Training experience in Communication/Networking domain at Client Roopang Infocare
Very good experience in CDMA and GSM Technique
Good understanding in IpV4& TCP/IP network/Ethernet Protocol
Strong Digital Technical knowledge
Took special training on VLSI and CMOS backhand undertaken by Vector India Pvt Ltd
T echnical Skills:-
Depth knowledge of Design process from design specification, defining architecture, RTL
Design & Functional Verification, synthesis, Physical design, Tape -out, Post Si-debug
Exposure & Analysis of STA(Static Timing Analysis)/Clock distribution/Primetime
Good Knowledge on Optimized Layout design maintaining DRC and LVS
Experience in one/more of the following system bus interfaces like AMBA-AHB/AXI,
PCI/PCIe, SATA, NAND Flash memory controller/Interface, etc
Experience and understanding of Signal Integrity
Experience in Block/IP/chip level synthesis, time closure & ECO flows
Expertise in FPGA Prototyping & validation
Experience in ARM based SOC bring up and debugging on FPGA/SOC platforms
Network Troubleshooting, Windows Troubleshooting (Windows/XP/vista/7/8)
Interact with prospective and existing clients to collect information about their issues and
provide proposed solutions.
Head responsibility for technical validity along with interoperability of solution.
Log the issues and resolutions in organization records.
Excellent team player with good inter-personal skills.
Quick decision making ability and Logical approach to problem sol ving.
Ability to work under pressure.
Desire to acquire new technologies and knowledge.
Strong Technical understanding.
Verification based Chip Validation (SOCs)
FPGA Prototyping and Debugging the design and STA analysis
Have Successfully Completed B.Tech In Electronics and Communication Engineering (ECE) from
Lovely Professional University-Punjab in the year 2012 with 8.46 CGPA (76.14%)
Diploma in Electronics and Telecommunication Engineering from IETE New Delhi in the year 2007
Matriculation from GSEB Gujarat in the year of 2001 with 84.57%
Advanced Training in VLSI (Back End – Front End) at Vector India Pvt Ltd Hyderabad with Live Projects
Project: RF Based Virtual Password Access
Description: I worked on Radio frequency based security system. Its Phenomenon that Password is virtually
changed round the clock. It Comprises logical algorithm that changes password periodically and stored in
memory. It Fully operated through RF module which generate 443 Mhz when low signal occurs password
T echnology: Wireless Communication
Key Finding: Its Robust security system that its password continuously changing round the clock at every
attempts generates new password.
Duration: JAN 2012-JUNE 2012
VLSI Based Projects
Project: Design and Simulation of Baud Rate Generator using UART serial Communication
Description: It Concentrates on developing a serial communication protocol including bus automatic baud rate
detection with selection and bit synchronization,frequency division according to the input clock. One for a single
clock at the beginning of the session, whic h is then maintained for the entire duration of the session (this one is
called "auto_baud.v"). And another version constantly tracks the incoming character,which allows changes for
the clock rate and or Baud rate of incoming characters to happen at anyti me & Baud rate will adjust when
Language & Tool : Verilog / XILINX ISE 12.3
Challenge Faced : Role of Frequency Divider in UART
Automatic Baud rate Detection
T eam Size: 2
Duration : DEC 2012- FEB 2013
Project: Dual Port RAM Verification
Description: Which allows multiple Reads and Writes to occur at the same time for Transmission of data unlike
in Single Ported RAM.
Key finding: Generates Test cases and Interface of Top level module, to monitor the test stimuli
Implemented the Dual port RAM using Verilog HDL implementing
Architected class based Verification environment using SV
Verified RTL module using SV
Worked on Verification environment
Generates the following module to create verification of the Design.
Generated the class based function or code coverage for the RTL design.
Language & Tool: VHDL & (System Verilog) Model Sim Altera 10.1b
T eam Size: 3
Duration: March 2013 – JULY 2013
Hands On Tools Experience:-
Xilinx ISE/Questa SIM/ Cadence NC sim/ModelSIM-Altera/Magma tools for physical verification
ASIC verification tools- DC compiler- Synopsys/Linux-Unix OS exposure/Cadence Virtuoso
Back Hand DFT Advisor – Mentor Graphics/Physical verification layout generation
Fast Scan test pattern generation/Test Kompress/BSD Architect/MBIST/LBIST/Yield Assistant
Always strive to discover something in digital era
Making science projects & electronics projects
To read Novels/Playing games/Debate/Play in RJs in radio entertainment
1st prize in science project in state zone in my schooling in solar System
1st Prize in Debate competition held in INTRA SCHOOL of LPU 2011
2 years of experience of managing MESS Department in LPU during 2009-2011
Secured 1st Prize in “ONE WORLD” cultural Event held at LPU November 2011
Successfully Organized “SEMIOTICS 2011” a research paper presentation seminar as an event
manager at LPU (LEET)
Full Name : Patel Chiragkumar Karasanbhai
Fathers Name : Patel Karasanbhai Valjibhai
Date of Birth : 19/12/1985
Languages Known : English/Hindi/Gujarati
Marital Status : Single
I consider myself familiar with Electronics & Communication Engineering aspects. I am also
confident of my ability to work in a team.
I hereby declare that information furnished above is true to the best of my knowledge.
Date: 25/04/2014 Signature
Place: Hyderabad Patel Chiragkumar