Design Engineer

Khushmit Pandya

Ariba PG '***',

Next to Reliance Mart,

Arekere Gate,

Bannerghatta Road, Email :

**********@*****.***

Bangalore-560076

Mo. +91-973*******

Career Objective

To work as a Verification/ Design Engineer in an organization where I can

utilize my technical skills for organizational development and my

professional career growth.

Summary of Qualifications

> Good understanding of the ASIC and FPGA design flow

> Experience in writing RTL models in Verilog HDL and

Testbenches in SystemVerilog

> Very good knowledge in verification methodologies

> Experience in using industry standard EDA tools for the front-end

design and verification

VLSI Domain Skills

HDL: Verilog

HVL: SystemVerilog

Verification Methodologies: Coverage Driven Verification

Assertion Based Verification

TB Methodology: UVM

EDA Tool: Questa sim and ISE

Domain: ASIC/FPGA Design Flow, Digital Design

methodologies

Knowledge: RTL Coding, FSM based design, Simulation,

Code Coverage, Functional

Coverage, Synthesis,

Static Timing Analysis, ABV

Professional Qualification

Maven Silicon Certified Advanced VLSI Design and Verification course

from Maven Silicon VLSI Design and Training Center, Bangalore

Year: December 2013

Bachelor of Engineering, L.C.Institute of Technology, Bhandu, Mehsana.

Gujarat Technological University,

Gujarat, India

Discipline: Electronics and Communication Engineering

Percentage: 6.76

C.G.P.A with 1st class

Year: May 2013

H.S.C. (10+2) : Shivashis Boarding School

Gujarat Secondary and Higher secondary Education Board

Percentage : 59 %

Year :May 2009

S.S.C. (10) : Kameshwar vidhyalaya

Gujarat Secondary and Higher secondary Education Board

Percentage: 77%,distinction

Year :May 2007

Experience

June 2012 - April 2013, ISRO(SAC), Ahmadabad, Gujarat

August 2013 - January 2014, Maven Silicon, VLSI Design and Training Center-

Bangalore

February 2014-GRID INDIA IT INNOVATION, Bangalore

VLSI Projects

AMBA AXI4 Protocol Verification using UVM

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Modelsim, QuestaSim -- Verification Platform

Description: The AMBA AXI protocol is targeted at high-performance, high-

frequency system and includes a number of features that make it suitable

for a high-speed submicron interconnects. The AXI protocol is burst-based.

Every transaction has address and control information on the address

channel that describes the nature of the data to be transferred. The data

is transferred between master and slave using a write data channel to the

slave or a read data channel to the master.

> Architected the class based verification environment using UVM.

> Verified the protocol using class based UVM Testbench.

> Generated functional coverage for the verification sign-off

AMBA AHB Protocol Verification using UVM

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools: Modelsim, QuestaSim -- Verification Platform

Router 1x3 - RTL Verification using UVM

HVL: SystemVerilog

TB Methodology: UVM

EDA Tools and Environment: Modelsim, Questa - Verification Platform

Description : The router accepts data packets on a single 8-bit port called

data and routes the packets to one of the three output channels, channel0,

channel1 and channel2.

.

> Architected the class based verification environment using UVM.

> Verified the RTL model using class based UVM TB..

> Generated functional and code coverage for the RTL verification sign-

off

RAM SOC - RTL Verification using UVM

HVL: System Verilog

TB Methodology: UVM

EDA Tools and Environment: Modelsim, Questa - Verification Platform

Description : The Design Under Test(DUT) fot this verification test bench

is RAM SOC.

It includes four instances of 4096 x 64 RAM chip

> Architected the class based verification environment using UVM

methodology.

> Verified the RTL module using the UVM class based TB.

> Generated functional and code coverage for the RTL verification sign-

off

Dual Port RAM - Verification using System Verilog

HVL: System Verilog

EDA Tools and Environment: Modelsim, Questa - Verification Platform

> Implemented the Dual Port Ram using Verilog HDL independently

> Architected the class based verification environment using system

Verilog

> Verified the RTL module using System Verilog

> Generated functional and code coverage for the RTL verification sign-

off

Router 1x3 - RTL Design

HDL: Verilog

HVL: Verilog

EDA Tools: Xilinx ISE Design Suite, Questasim.

Description : The router accepts data packets on a single 8-bit port called

data and routes the packets to one of the three output channels, channel0,

channel1 and channel2.

> Architected the design and described the functionality using Verilog

HDL.

> Verified the RTL model using Verilog.

> Generated code coverage for the RTL verification sign-off

> Synthesized the design

Ground Checkout Unit(GCU) For Navigation Signal Generation Unit(NSGU) (at

ISRO(SAC))

> Design and Development of Ground Checkout Unit (GCU) to test and

validate onboard Navigation Signal Generation Unit (NSGU)

> It includes Telecommand Transmission to Navigation Signal Generation

Unit (NSGU) and NSGU output signal acquisition & verification.

Declaration

I hereby declare that the information given here with is correct to

best of my knowledge and I will responsible for any discrepancy.

Place :Bangalore Khushmit

Pandya

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