ASIC Verification Engineer

PAVAN KUMAR T V [pic]

#***, *** *****, *** : +91-720*******

13th Main, Sector 5,

HSR Layout, Email: ***************@*****.***

Bengaluru-102.

Objective:

Seeking a position and environment to utilize my skills and abilities in

the VLSI industry that benefits company in the best manner and offers

professional growth while being result-oriented, innovative.

Profile Summary

. ASIC Design Verification Engineer Trainee with 2 years of experience

in System Verilog & UVM.

. Experienced in Developing Test & Verification Plans, Writing Test

Bench Components, Writing Functional Coverage, Analyzing Code

Coverage & Writing Assertions.

. Hands on EDA tools (Modelsim, MPsim, Questasim, Rivera, Cadence ius,

VCS).

Technical skills:

Hardware Language : VHDL, Verilog, System Verilog, SVA,

Trek

Tools Simulation : ModelSIM v10.0d, Questa SIM

v10.2c,

VCS-MX v10.9.3, Cadence SimVision v12.2,

Riviera-Pro v2013.06, Trek v4.0.7

Tools Synthesis : Xilinx ISE 13.1i, ALTERA Quartus

II 12.0,

Synplify

Verification Methodologies : UVM, UVM_RAL

Protocols and Standard : AMBA (v2.0,v3.0) - APB, AHB, I2C,

SPI

Programming Languages : C, C++

Script language : Perl

Operating System : Windows XP/7, Linux/Unix

Application Software : MS Office Package(Word,

PowerPoint, Excel )

Work Experience:

* ASIC Design And Verification Engineer - Trainee :

CVC Pvt. Ltd. Agara, Bengaluru. Mar 2012

- Feb 2014

Projects:

1. Verification of AMBA APB3.0 Interface Protocol

Duration: 3 Month (Mar 2012 - May 2012)

Description: The APB is part of the AMBA 3 protocol family. It

provides a low-cost interface that is optimized for minimal

power consumption and reduced interface complexity. The APB

interfaces to any peripherals that are low-bandwidth and do

not require the high performance of a pipelined bus

interface. The APB has un-pipelined protocol. All signal

transitions are only related to the rising edge of the

clock to enable the integration of APB peripherals easily

into any design flow. Every transfer takes at least two

cycles. It is used to provide access to the programmable

control registers of peripheral devices.

Role: Implemented Design module in Verilog and Verification using

System Verilog and developed Driver, Monitor, Sequencer in UVM

Methodology.

Environment: UNIX, Verilog, System Verilog, UVM, Questa SIM v10.1,

MPSIM

2. Verification of AMBA 3.0 Advanced Hi-Speed Bus[AHB-Lite] - SLAVE

Duration: 4 Months (Jun 2012 - Sept 2012)

Description: AMBA AHB-Lite addresses the requirements of high-

performance synthesizable designs. It is a bus interface

that supports a single bus master and provides high-

bandwidth operation.

Role:

. Involved in creating TB in System Verilog.

. Developed verification environment in UVM.

Environment: UNIX, Verilog, System Verilog, UVM, Questa SIM v10.1

3. Verification of a FIFO

Duration: 3 Months (Oct 2012 - Dec 2012)

Description: FIFO (First-in First-out) is a stack memory to which data

is pushed in and popped out whenever required. A Stack

pointer is used as there is no addressing of locations. The

data pushed first should be the one to receive when popped.

Role:

. Involved in creating TB in System Verilog.

. Developed verification environment in UVM.

Environment: LINUX, Verilog, System Verilog, UVM, Questa SIM v10.2

4. Verification of APB-Memory_Controller_with_RO_WO

Duration: 3 Months (Jan 2013 - Mar 2013)

Description: AMBA APB is interfaced with the Memory controller that

has Read-Only, Write-Only, and Reserved locations. Writing

to RO or reading from WO or any operation in Reserved will

through an error respective to the Spec.

Role:

. Involved in creating TB in System Verilog.

. Developed verification environment in UVM.

Environment: UNIX, Verilog, System Verilog, UVM, Cadence SimVision

v12.2

5. Verification of APB-SPI.

Duration: 4 Months (Apr 2013 - Jul 2013)

Description: APB with SPI (Serial Peripheral Interface) Master core,

Synchronous serial interfaces are widely used to provide

economical board-level interfaces between different devices

such as microcontrollers, DACs, ADCs and other.

Role:

. Involved in creating TB in System Verilog.

. Developed verification environment in UVM.

Environment: UNIX, Verilog, System Verilog, UVM, Questa SIM v10.2

6. Client Engagement

On-site client : BROADCOM, Bangalore.

Duration : 1 Month (Aug 5 2013 - Sept 5 2013)

Description : Corporate Training.

Language : Verilog, System Verilog, System

Verilog Assertion, UVM.

Scripting language : PERL.

Tools used : CADENCE -IUS.

Responsibilities : Role was to Support the team for any kind of

problems on the provided Labs or the project given to

them.

7. Verification of APB-I2C using UVM and UVM RAL.

Duration: 2 Months (Sep 2013 - Oct 2013)

Description: APB with I2C is a two-wire, bi-directional serial bus

that provides a simple and efficient method of data exchange

between devices. It is most suitable for applications

requiring occasional communication over a short distance

between many devices.

Role:

. Developed verification environment in UVM.

. Using the developed verification environment in UVM, a RAL model

was added and tests were written accordingly.

Environment: LINUX, UVM, Riviera-Pro v2013.06.

8. Client Engagement

Client : ALDEC.

Duration : 1 Month (Nov 2013)

Description : Riviera Pro (Upgraded Version) Tool

Validation.

Language : System Verilog.

Tools used : Riviera-Pro v2013.06.

Responsibilities : Role was to create test cases in System

Verilog for Coverage.

9. Verification of APB-SPI using UVM RAL

Duration : 1 Months (Dec 2013 - Jan 2014)

Description : APB with SPI (Serial Peripheral Interface) Master core,

Synchronous serial interfaces are widely used to provide

economical board-level interfaces between different devices

such as microcontrollers, DACs, ADCs and other.

Role :Using the developed verification environment in UVM, a RAL

model was added and tests were written accordingly.

Environment : LINUX, UVM RAL

10. Client Engagement

On-site client : KARMIC, Manipal.

Duration : 11 Days (Dec 21 2013 - Jan 1 2013)

Description : Support the Team.

Language : System Verilog, System Verilog Assertion, UVM.

Tools used : CADENCE -IUS.

Responsibilities : Role was to Support the team for any kind of

problems on the

provided Labs or the project given to them.

11. Verification of APB-SPI using TREK Gen2.

Client : BREKER SYSTEMS

Duration : 1 Months (Jan 2014 - Feb 2014)

Description : APB with SPI (Serial Peripheral Interface) Master core,

Synchronous serial interfaces are widely used to provide

economical board-level interfaces between different devices

such as microcontrollers, DACs, ADCs and other.

Role :

. Developed System Verilog TB and attached Trek

environment to it. Tests were written accordingly.

Environment: LINUX, Trek, Trek v4.0.7.

Academic Project:

> Course Thesis: Automatic Speaker Recognition using Matlab.

> Automatic Speaker Recognition System is a system which recognizes the

person according to his voice, no matter what he speaks. Each voice is

differentiated based on the parameters of voice such as Pitch of the

voice, Voice Harmonics, Voice Frequency etc. This we have tried to

implement using Matlab, wherein a test voice is given and it is matched

with a previously stored database. As to make this more interesting it is

worked both on the basis of VECTOR QUANTIZATION (VQ) and ARTIFICIAL

NEURAL NETWORKS (ANN) Methodologies, and thereby comparing both

Methodologies on the basis of their output in percentages.

Academic Qualification:

. B.E in Electronics & Communication from H M S Institute Of Technology,

Tumkur, affiliated to VTU in 2011.

. 10+2 from Jawahar Navodaya Vidyalaya, Tumkur, affiliated to CBSE Delhi

in 2007.

. 10 from Kendriya Vidyalaya, Tumkur, affiliated to CBSE Delhi in 2005.

Personal Profile

> Date of Birth : 26.10.1989.

> Father's name : VijayaKumar.

> Nationality : Indian.

I hereby declare that the above information is true to best of my knowledge

and belief.

PLACE: BENGALURU.

PAVAN KUMAR TV

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