Design Electrical

ARAVINDAN SESHADRI

***, **** ****** **** **: 972-***-****

Richardson, Texas-75080 *********.***@*****.***

OBJECTIVE: To obtain a challenging full - time opportunity in the field of ASIC/Digital design.

SKILLS SUMMARY:

Design & Verification:

Verification IP for UART (UVM & SV)

1K SRAM

CMOS Operational Amplifier

23*23 bit multiplier

Front to back end IC design for yawing and pitching of wind mill

Physical design:

DRC and LVS check for SRAM, standard cells

Place and route for standard cells.

Simulator Tools:

Cadence - Virtuoso layout and Schematic editor, HSPICE

simulator, Encounter tool (P&R), cadence Assura,

Xilinx ISE 10.1

AWR Microwave Office

Verification Language

System Verilog OVM, UVM

Languages

C, C++,Verilog HDL, PERL Scripting, System Verilog

Operating Systems

UNIX, Solaris, Linux

Protocols

I2C, UART, CAN, APB,

EDUCATION:

GPA 3.43/4.0 Aug 2012 – May 2014

Master of Science (Electrical Engineering)

University Of Texas at Dallas

GPA 8.3/10.0 Aug 2008– June 2012

Bachelor of Engineering (Electrical&Electronics)

Anna University, Chennai, India

RELEVANT COURSES:

Advanced VLSI Design

VLSI design

Analog integrated circuit design

Advance digital logic

RF and Microwave circuits

RF and Microwave Amplifier design

RF and Microwave systems

Digital Signal Processing

Computer architecture

Testing and Testable design

ARAVINDAN SESHADRI

601, West Renner Road Ph: 972-***-****

Richardson,Texas-75080 *********.***@*****.***

PROJECTS:

● Verification IP for UART using UVM: Designed a System Verilog UVM environment to test the UART

protocol on the excising RTL design. The testing were simulated using VSC simulator and the verification of

the RTL design was done.

● 1K SRAM Design: Designed a 1K SRAM schematic and layout (hSpice, 130nm) using Cadence

tools.DRC LVS check. 6-Tansistor SRAM Memory cell was used for storing the Bit. The necessary Row

decoder, the column decoder and the pre-charge circuits for the SRAM were designed. The circuit was

optimized for power and speed.

● 23*23 Bit Multiplier: Designed a 2 3 * 2 3 b i t m u l t i p l i e r using booth-2algorithm (hSpice, 130nm)

using Cadence tool. Ripple Carry Adder (RCA) was used for addition. The multiplier was designed to handle

negative multiplicand.

● Front-to-Back IC Design On Dynamic Operation of Windmill Yawing and Pitching System:

Designed Standard cells (NAND, NOR, INVERTER, MUX, D-FLIP FLOP, AOI211) (hspice, 130nm) using

Cadence. Design Rule Check (DRC) and Layout versus Schematic (LVS) Check. Using the standard cells a

library was created and Encounter tool was used for placement and routing of the cells. Final DRC and LVS

were checked for the chip.

● A Fast-Settling, High-Gain Op-Amp: Designed a Fast-settling, DISO Operational Amplifier to be used

in a highly linear voltage buffer using the cadence Analog artist. A single -stage folded cascade Op-amp

architecture was adopted for the design. Challenge in the work was the trade-off between the 60-dB gain that

dictates long-channel devices and the fast settling time of 10 ns that requires short-channel devices for high-

speed operation.

● Remote Control of GOT Missile Guidance: Designed a Receiver and Transmitter model using AWR

Microwave office for Missile guidance system. The uplink frequency was set at 8GHz and the downlink

frequency was set at 7.5GHz.

● Final year thesis on “ADOLF-AeroDynamic Operations’ Leverage in FPGA”: Designed a single FPGA

chip to incorporate the activation of the Ailerons, Stabilizer, and Rudder of an aircraft. The comple te code was

written in Verilog perform. Xilinx simulator was used to simulate results and to dump them into the FPGA

Spartan 3E board. The complete working model was demonstrated with the FPGA chip as the processor. The

challenge in the work was the synchronization of frequency of the MEMS sensor with the clock frequency of

the FPGA board.

● 16-BIT Arithmetic and Logical Unit (ALU): Designed ALU model using a FPGA chip. The complete

coding set was written using Verilog HDL language incorporating basic operations like Addition, Subtraction,

logical AND, OR, NOT, increment, decrement, left rotate, right rotate, left shift, right shift. The results were

simulated in Xilinx 10.1 and implemented on Spartan 3E board.

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