Engineer Project
Resume:
DASARI ARJUN VASUDEVA MURTHY
Email: ***********@*****.***,***********@*****.*** Phone: (M) +91
Flat No: 104, KVR Encalve, Anjaneyapeta 3rd lane, Amaravathi Road,
Guntur, Andhra Pradesh -522007
To work in an innovative and stimulating environment that would facilitate
the maximum utilization and application of my broad skills and expertise in
making a positive difference to the organization
Profile At Glance
< Young, energetic and result-oriented M.S (VLSI-CAD) & B.E (Electronics
& Communications) professional offering 1 year of experience as
Verification Engineer (Intern) in Semiconductor/VLSI/EDA
< Demonstrated excellence in tackling the issues related to Functional
Verification, IP & SOC Verification, Digital Design & Verification
< Experienced professional with superior ability to motivate personnel
and enhance the overall efficiency, performance, and compliance with
standard procedures and regulations
< Keen ability to recognize and implement streamlined processes that
reduce errors and improve operational quality and efficiency
< Excellent interpersonal and man-management skills with the ability to
handle multiple projects and motivate large cross-functional teams
< Capable of delivering success in a complex project with scope for
learning and challenge
Technical Proficiencies
< Operating Systems: LINUX Red Hat, WINDOWS
< Languages: Verilog, SystemVerilog, C, C++, PERL
< Methodology: UVM Methodology
< Tools: Xilinx, Quartus, BSPICE, HSPICE, Magic, EMANAGER,
Simvision
< Bus protocols: AMBA-AXI, PCI, ST Imaging Bus Protocols
< Simulators: VCS, NCSIM
Core Competencies
~ Digital Design ~ Verilog ~ IP & SOC Verification ~ Functional
Verification ~
Professional Contour
ST Microelectronics Private Limited, Greater Noida
(Jul '12 - Jun '13)
Verification Engineer - Intern
Key Deliverables:
o Stabilizing the Various Imaging IP's in SV -UVM Environment
o Responsible for formulating Testcases for the IP's, running
Regressions
o Inspecting Functional Coverage and achieving 100% coverage
o Reporting the functionality of IP's
o Involved in formulating the Test Plan
Key Achievements:
o Successfully verified more than 10 Imaging IP's
o Successfully achieved 100% Functional Coverage
o Wrote Testplans
Projects Handled:
Methodology of IP Quality
Location: ST Microelectronics, Greater Noida
Duration: Jul '12 - Jun '13
Environment: UVM, C/C++/Verilog
Description: Image signal processing algorithms are developed and
evaluated using Reference models before RTL implementation.
After finalizing the algorithm, Reference models are used as a
golden model for the IP development. To increase the re-use of
design effort, the common bus protocols are defined for internal
register and data transfers. A pool of such configurable image
signal processing IP modules are assembled together to satisfy a
wide range of complex video processing SOCs.
Key Deliverables:
o Stabilizing the IP environment in UVM Methodology
o Involved in developing Test cases for IP's
o Running Regressions and achieving 100% functional Coverage
Front -End Development Tool
Tools: Java Script & PHP
Description: This is an encapsulation of all the scripts required to
perform basic tasks. It is developed to provide ease to user, so
that he can perform all the basic tasks required at the front
end from this software
Project Experience
#1:
Avionics: Cockpit Display using GL Studio
Location: Trident Infosal Private Limited, Benguluru
Duration: February - April 2011
Tools: GL Studio
Description: The main aim of the project is to design the electronic
system using human machine interface tool GL-Studio used in
avionics Cockpit. Avionics system is used in wide variety
of different application ranging from flight control,
instrument to navigation and communication. This system can
be generated using higher end graphics which are suitable
for any application in aircrafts where safety is critical.
Area of Application: Cockpit in all modern avionics.
Key Deliverables:
o Involved in designing and implementing the design using GL Studio
software
o Accountable for analyzing, Documentation and report Presentation
#2:
Implementation PCI-CONTROLLER using Verilog
Tools: Xilinix
Language: Verilog
Description: PCI bus is a high performance 32 and 64 bit bus used as
interconnect between the highly integrated peripheral
controller components. The arbiter decides on the basis of
Round-Robin technique, which Master go to the request of
the bus whenever there is a data to be transferred to
particular slave or to read from the slave. It was achieved
by different mode in which Master will be working like
memory read memory write and memory I/O modes. The Woking
of Master in different modes were coded in Verilog and the
simulation results were verified
#3:
Implementation of AMBA AXI
Tools: VCS
Language: System Verilog
Description: The project involves implementation of AMBA AXI using
System-Verilog. In this project, we implemented one master
and three slaves
Academia
M.S (VLSI-CAD) from MCIS, Manipal University in 2013 with 8.31 CGPA
B.E (Electronics & Communications) from SCSVMV University in 2011 with 8.14
CGPA
Intermediate from Narayana Junior College in 2007 with 83.5%
X from NSM Public School in 2005 with 67.7%
Personal Vitae
< Attended 1 Week In-plant training programme at Prasar Bharathi in
Chennai
< Visited High Power Transmission Doordarshan Kendra in Kodaikanal,
TamilNadu
< Attended 2 days FPGA workshop conducted by ENIXS Technologies, Trichy
Date of Birth: 18th June, 1990 Languages Known: English, Telugu,
Hindi and Tamil Reference: Available upon request
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