VLSI Design and Verification Engineer

CURRICULUM VITAE

Hiren Tada

E-mail: *********@*****.***

Mobile: +91-812*******

Entry level positions as Design/Verification Engineer preferably in ASIC/FPGA domain.

OVERVIEW

• Good understanding in Digital logic design & Electronics fundamentals

• Good understanding of the ASIC/FPGA design flow

• Experience in Verilog HDL to write synthesizable RTL, self-checking test benches&

Test benches in SystemVerilog

• Very good knowledge on Verification methodologies(UVM)

• Experience in using industry standard EDA tools for the Front-end Design and Verification

PROFESSIONAL QUALIFICATIONS

Maven Silicon Certified Advanced VLSI Design and Verification course

From Maven Silicon VLSI Design and Verification Training Center, Bangalore

Year : September 2013-February 2014

ACEDEMIC QUALIFICATIONS

Bachelor of Engineer in Electronics and Communication 2013

Government Engineering College Modasa,

Gujarat Technological University, Gujarat, India

CGPA : 6.4

Higher Secondary Education 2009

Shree Sardar Patel Vidhya Mandir - Mavdi, Rajkot

Percentage : 74.20 %

Secondary Education 2007

Shree Sardar Patel Vidhya Mandir - Mavdi, Rajkot

Percentage : 74.62 %

TOOLS&TECHNICAL SKILLS

HDLs : Verilog

HVL : System Verilog

Verification

Methodologies : Coverage Driven Verification, Assertion Based Verification

TB Methodology : UVM

EDA Tools : Modelsim and Xilinx-ISE

Domain : ASIC/FPGA Design Flow, Digital Design methodologies

Knowledge : RTL Coding, FSM based design, Simulation, Code Coverage,

Functional Coverage, Synthesis, Static Timing Analysis, ABV

Programming

Languages : C, OOPs, Assembly Language in 8085 & 8051

Tools/Softwares : MATLAB, Keil,

Operating systems : Windows & Ubuntu

VLSI PROJECTS

GPIO IP Core Verification

HVL : System Verilog

TB Methodology: UVM

EDA Tools : Modelsim, Questa-Verification Platform

Description :

The GPIO IP core is user programmable general-purpose I/O controller. Its use is to

implement functions that are not implement with the dedicated controllers in a system and

require simple input and/or output software controlled signals.

Architected the class based verification environment using UVM

Verified the RTL module using SystemVerilog

Verification of the RTL module using UVM

Generated Functional coverage for the RTL verification

Router 1x3 – RTL design and verification

HDL : Verilog

HVL : SystemVerilog

TB Methodology : UVM

EDA Tools : Modelsim, Questa-Verification Platform and Xilinx-ISE

Description :

Architected the design and described the functionality using Verilog HDL.

Verified the RTL model using Verilog.

Generated Code coverage for the RTL verification sign-off Synthesized the design

Architecting the class based verification environment using UVM

Verification of the RTL module using UVM

Generation of functional coverage for the RTL verification

Dual Port RAM – RTL design and verification

HDL : Verilog

HVL : SystemVerilog

EDA Tools : Modelsim, Questa-Verification Platform and Xilinx-ISE

Description :

Implemented the Dual Port RAM using Verilog HDL independently

Verified the RTL module using Verilog& SystemVerilog

Architecting the class based verification environment using UVM

Verification of the RTL module using UVM

Generated Code coverage & Functional coverage for the RTL verification sign-off

Synthesized the design

ACEDEMIC PROJECTS

1) CENTRALIZED MONITORING SYSTEM FOR CALL TAXIES (7th & 8th semester)

2) Digital Voltmeter Using 8051 Micro Controller (5th semester)

ACEDEMIC INTERNSHIP

Pursued training from ETERNITY GREEN (GANDHINAGAR) (7th & 8th semester)

Project : CENTRALIZED MONITORING SYSTEM FOR CALL TAXIES

PERSONAL DETAILS

Name : Hiren Naranbhai Tada

Date of Birth : December 25, 1991.

Linguistics : English, Hindi and Gujarati

100, Navo Ploat Vistar,

Address :

Dhundhoraji, Tal :- Kalawad,

Dist:- Jamnagar, Gujarat-361160

DECLARATION

I hereby declare that the above mentioned information is correct up to my knowledge and

I bear all the responsibilities for the correctness of the above mentioned particulars.

Place: Bangalore (Hiren Tada)

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