Design Engineer Engineering

Yateesh Kumar Sharma

***A, Sri lakshmi Phone. 767-***-****

Venkateshwara, Email.yateesh.gbpec@gmail

Kundanhalalli gate, .com

bangalore- 560037

Objective

Seeking full time position in an organization that utilizes my skills and

abilities and offers professional growth while being resourceful and

innovative.

Experience

1. Organization: STMicroelectronics, Onsite for Masamb Electronic systems

Duration: March 2013-June 2013

Designation: Design Engineer (Standard Cell Layout)

Skills and Responsibilities:

. Developed Standard cell layouts for multiple technologies till 28nm

FDSOI.

. Sound knowledge of DRC, LVS, Fingering, Flipping, and related

design techniques.

. Responsible for IP packaging of standard cell libraries.

. Possess good team working spirit and enthusiasm to learn new

things.

2. Organization: STMicroelectronics, Onsite for CMR Design Automation

Duration: July 2012 - September 2012

Designation: Design Engineer

3. Organization: Vivekanand Institute of Technology & Science, Ghaziabad

Duration: August 2009 - August 2010

Designation: Lecturer

Professional Qualification

Course : Master of Technology (2010-2012)

Major : VLSI Design

Institut : National institute of Technology (NIT), Kurukshetra

e

CGPA : 8.67

Course : Bachelor of Engineering (2005-2009)

Institut : Govind Ballabh Pant Engineering College (a State govt.

e engineering college),

Pauri-Garhwal Uttarakhand.

Universi : H. N. B Garhwal University, Srinagar-Garhwal, Uttarakhand.

ty

% Marks : 72.2%

Skills and Knowledge set

Operating Systems : Linux (RedHat, Ubuntu), MS-Windows(XP/Vista/7/8)

Tools exposure : Cadence Virtuoso, Calibre (Mentor Graphics), Xilinx

ISE Design Suit, ModelSim, Design Architect IC

Hardware (Mentor graphics)

Description :

language

Verilog HDL

Achievements

Qualified GATE 2011 with 93.10 percentile (AIR-9544).

Qualified GATE 2010 with 95.10 percentile (AIR-5126).

Qualified GATE 2009 with 91.95 percentile (AIR-3397).

Related Courses

> Analog Integrated Circuits

> Digital Electronics

> Digital CMOS Integrated Circuits

> Digital System design with Verilog HDL

Academic Projects

> ECG signal classification on MATLAB.

First preprocessing of ECG signals is done to reduce the effect of noise.

Then ECG beats are separated from each other in beat detector. In feature

extraction, such information from the ECG beats is extracted so that on

the basis of that information discrimination between different types of

ECG beats can be done. Multi-layer feed-forward neural network has been

employed for classification of four types of ECG beats.

Platform: MATLAB

> Designed and simulated 8 bit Arithmetic and logic unit.

Different functional block of ALU such as adder, subtractor were first

simulated using ModelSim then these block are connect together using a

data bus.

Declaration

I hereby declare that the details mentioned above are correct to the best

of my knowledge.

Date: (YATEESH KUMAR SHARMA)

Contact this candidate