Engineer Project

SACHIN RAJ AGGARWAL

ENGINEER VERIFICATION >*+yrs. with TRANSWITCH;

1+ yrs. as Engineer; M.Tech. (VLSI Design) from C-DAC, Noida

e-mail Id -

Contact Phone **************@*****.***

Mobile - +91-928*******

+91-925******* *********@*****.***

Aspiring to pursue assignments in the domain of Semiconductor &

Electronics engineering with a growth oriented organization of repute

and to Explore VLSI Design - ASIC Design & Verification

Career Profile

< 1+yrs. ASIC Verification - SystemVerilog testbenches using UVM/VMM

methodologies, RTL Coding & standard protocols as I2C, SPI

< Projects Undertaken- Quad SPI verification IP using UVM; Verification IP

of I2C Slave in UVM & SystemVerilog; Triton (HDMI Port) etc.

< Worked on Backend projects i.e. - Single Bit Dual Port SRAM Cell Design

and on Frontend projects i.e. AMBA AHB bus interface, Timer, FIFO.

< M. Tech. (VLSI Design) 2011-13 & B. Tech. (Electronics & Comm. Eng.) 2006-

10

< Adaptable and a quick learner; possesses skills to work under pressure.

< Possess strong management, communication & interpersonal skills.

Work Experience (2+yrs.)

Designation Organization Duties Joining Date Remarks

Engineer M/s.Transwitch Verification March, 2013 System

Trainee India Pvt. Ltd., to date Verilog,

New Delhi UVM/VMM

Graduate INCISE INFOTECH VLSI Aug.,10-July VLSI, Verilog,

Engineer Pvt. LTD., NOIDA Designing,11 EDA Tools

Tr.

Technical CETPA INFOTECH train June,10-July @

Trainer Pvt. LTD., NOIDA students in,10 Rs.10,000/-p.m

C/C++ .

Technical Skills / IT forte

HDLs / HVL SystemVerilog, Verilog, VHDL

METHODOLOGY UVM; VMM & OVM

Scripting Languages Perl, Tcl

VLSI/EDA TOOLS Vcs (Synopsys), Model Sim (Mentor Graphics),

(FRONTEND) Questa (Cadence),

VLSI / EDA TOOLS Tanner EDA Tools, IC Station(Schematic, Layout

(BACKEND) Editor, LVS, DRV, SDL), Matlab

Operating Systems Linux(CentOS-5.2), Unix (basic), Windows XP/ 2000

Standard Protocols I2C, SPI OTHER SKILLS- C/C++, RTL CODING

Academics

Gate qualified (Gate examination 2011 qualified)

YEAR OF PASSING GATE SCORE GATE PERCENTILE ALL INDIA RANK

2011 456 94.80 7126

EDUCATIONAL QUALIFICATIONS -

Degree Period Institute Percentage

(University/Board)

M. Tech. (VLSI) GGSIPU, 2011-13 C-DAC, NOIDA 75.63%

Delhi

B. Tech. (ECE) GGSIPU, 2006-10 HMRITM, Delhi 70.48 %

Delhi

XII (under 10+2 ) CBSE 2004-05 SBKV Sr. Sec. 85.6 %

School

X (under 10+2) CBSE 2002-03 SBKV Sr. Sec. 65.8 %

School

Projects Handled Currently (with Transwitch) -

Title (Project Quad SPI verification IP (using UVM)

- 1) (verification using Flash Memory & IMEM for DMA

purpose)

Used - Vcs (Synopsys) [pic] SystemsVerilog [pic]

Tools/skills UVM Methodology

Testbench [pic] Linux

[pic] Flash Memory

Title (Project Verification IP of I2C Slave in UVM & System Verilog

- 2) etc

Used - Vcs (Synopsys) [pic] SystemsVerilog [pic]

Tools/skills UVM Methodology

Testbench [pic] Linux

Title (Project Triton (HDMI Port) - running regression & analyzing

- 3) reports

Thesis/Projects

M. Tech Projects

M. Tech MAJOR Project

Title Design of Serial Peripheral Interface (SPI) Slave

for C-DAC, Noida

Used - Tools / Modelsim (Mentor Graphics) [pic]

Verilog

Operating Sys. RTL coding, testbench [pic]

Linux / Windows

Project The Direct Memory Access (DMA) allows accessing of

Description system memory for reading and writing purposes

without any intervention of CPU/Processor.

Implemented Features:[pic] Pipelining technique has

been introduced between DMA & SPI [pic] Simulation

written for the DMA SPI Interface system [pic]

Waveforms generated and analyzed.

M. Tech MINOR Project

Title Single Bit Dual Port SRAM Cell Design for C-DAC,

Noida

Used - Tools / IC Station (Mentor Graphics) [pic] LVS,

Schematic

Operating Sys. Layout Editor [pic]

Linux / Windows

Project 1-bit Dual Port SRAM Cell designed & developed along

Description its - Sizing, Optimization, Delay Analysis, Layout

creation for 8T SRAM Cell, LVS, DRV Check, RC

extraction. Implemented Features: [pic] Area

efficient [pic] Low Power Consumption [pic] Can

be configured up to Transistor Level.

B. Tech Projects

B. Tech Major Project for GGSIP University

Title (Project Infra Red Based Obstacle Avoiding Robot

- 1)

Language/Skill C, C++; Embedded System; using 8051 Microcontroller;

s IR trans-receiver; & used - u-vision Keil for

coding.

Title (Project Lead Acid Battery Charger With Voltage Analyzer

- 2)

Title (Project Electronic Alarm Clock using Verilog with HP

- 3)

Awards & Recognitions

In Professional Field -

* Achieved "quick learner and fast ramp" recognition from wherever I

have worked.

* Attended workshop on Semiconductor EDA Tools by Cadence at Park, New

Delhi

* Attended Advanced Analog & RF workshop by IEEE at ST Microelectronics,

Gr. Noida.

* Got appraisals & accolades from Management & Students while training

them.

In Academic Field -

* Won IInd Prize in School XIIth class with 4 distinctions and 2 above 90%

marks.

* Won & Participated in several National Olympiads for Science, Cyber &

Math's.

* Won Certificate of merit from class I, class VII, VIII and XII during

schooling.

In other Field -

* Been excellent & active chess player during schooling & won many prizes

and certificates including Sub-Junior Championship, Inter School

Championship, and Open Rating Championship etc. & represented School and

Zone at State Level.

* Represented college for chess in Intra College Sports Competition of

GGSIP University 2007, 2008. 2009 & 2010 and won 2nd & 3rd Prizes

Personal Details

Gender MALE Marital Status Single

Date of Birth 26.10.1987 Nationality Indian

Father's Name RAJESH AGGARWAL Mother's Name PRABHA AGGARWAL

Hobbies Playing Chess - my most favorite hobby specially

blitz

Online Games - playing all kinds of action & puzzle

games

Watching Movies - to watch action, comedy &

thrillers

Listening Music - to all kinds of music

Strength [pic] Simple & Sober

[pic] Adaptable

[pic] Skilled to work under pressure

[pic] Sincere & Honest

[pic] Strong Managerial & Interpersonal Skills

[pic] Quick learner

Contact H.No.- 3 / 72, 3rd Floor, Nirankari Colony, Delhi -

Address 110009. India

I hereby declare that the above mentioned information is correct up to

best of my knowledge and I bear the responsibility for the correctness of

above mentioned particulars.

(Sachin Raj Aggarwal)

Date : 20th March, 2014 Ph.

(mobile): 928-***-**** - 925*******

Place : New Delhi (India) e-mail id -

**************@*****.***

*********@*****.***

[pic]

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