Cover Letter System
Resume:
SATHISH KUMAR D
Mobile: (0-953*******
Email: acdr10@r.postjobfree.com
Jayanagar 1st Block East,
Byrasandra,
Bangalore - 560 011.
Objective
Seeking a challenging contract and fulltime position in
Esteemed Organization where my skills and experience will greatly enhance
the company's success and my personal growth.
Career Summary
> Good understanding knowledge of FPGA design flow
> Good knowledge of Digital Circuits
> Working Experience in writing RTL models in Verilog HDL and
Test benches in System Verilog
> Working Experience in using industry standard EDA tools
> Project Documentation Skills
Core Competencies
HDLs : Verilog, VHDL and Mixed HDL
HVLs : System Verilog
EDA Tool : Lattice Diamond, Xilinx ISE and Modelsim.
Verification
Methodologies : Constrained Random Coverage Driven Verification &
Functional Coverage
TB Methodology: VMM from Synopsys
Domain : Digital Design methodologies, ASIC/FPGA Design Flow.
Knowledge : RTL Coding, FSM based design, Simulation, Synthesis,
Code Coverage, Functional Coverage,
Static Timing Analysis.
Professional Qualification
Education Year of % of
University/Board Institution Marks
Passing
Anna C.Abdul Hakeem 2011 75
B.E.(E.C.E) University, College
Chennai
Of Engg & Tech,
Vellore.
X Std State Board Govt. Hr. Sec. 2005 82.6
School,
Vellore.
XII Std State Board Don Bosco Hr. Sec. 2007 84.41
School,
Katpadi, Vellore.
Industry Work Experience:
> Relevant Experience: Currently working in Shirvanthe Technologies
Private Limited, Bangalore as a Project Engineer - VLSI Design
Engineer.
Projects at Shirvanthe Technologies Pvt Ltd
Individual Projects Handled
1. I2C - Master Core - RTL Design and Verification(Pursing)
HDL: Verilog
HVL: Verilog Test bench
EDA Tools: ISE
> Implemented the above projects using Verilog HDL independently
> Verified the RTL model using Verilog Test bench.
> Generated code coverage for the RTL verification sign-off
> Synthesized the design
2. I2C - Master/Slave Controller with APB Interface -RTL Design
HDL: Verilog
HVL: Verilog Test bench
EDA Tool: ISE
> Implemented the above projects using Verilog HDL independently
> Verified the RTL model using Verilog Test bench.
> Generated code coverage for the RTL verification sign-off
> Synthesized the design
3. UART- IP Core - Design And Verification(Pursing)
HDL: Verilog
HVL: System Verilog
EDA Tools: Xilinx, Lattice Diamond, Modelsim
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog
> Generated functional and code coverage for the RTL verification sign-
off
4. Real Time Clock (Design and Verification) & Router 1x3 - Verification
HDL: Verilog
HVL: System Verilog
EDA Tools: Modelsim, Questa -Verification Platform
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog,UVM
> Generated functional and code coverage for the RTL verification sign-
off
Extra-Curricular Activities
> Got Appreciation Certificate for donated My Blood to Transfusion
Medicine Centre (Blood Bank) In NIMHANS (National Institute of Mental
Health & Neuro Sciences) Hospital, Bangalore On January 9th 2012.
> Attended Accellera System Verilog Online Workshop, on 13th January
2013.
> Attended Seminar - 1 on Microcontrollers & Sensors, ST
Microelectronics Technology Day - 2013, In Taj West End, Bangalore on
19th September 2013.
> Maven Silicon Certified Advanced VLSI Design and Verification course
From Maven Silicon VLSI Design and Training Center, Bangalore Year:
July 2011 - January 2012.
Strengths
> Self Confident,Self Motivation & Self Directed
> Hardworker
> Good team player
> Willing to learn
Personal Profile
Name : D.Sathish Kumar
Father's name : D.Dasarathan
Mother's name : D.Jayanthi
Date of Birth : 4th Jan 1990
Age : 23 years
Gender : Male
Marital Status : Single
Nationality : Indian
Communication Proficiency : English, Tamil and Kannada
Skills : Fast learner,
Interpersonal skills
Interest's : VLSI technology and Physical Exercise's
Hobbies : Physical Exercise's &
Playing Cricket
Experience : 6 months
Address for comm. : No.25, 2nd Cross, 4th Main,
Byrasandra,
Jayanagar 1st Block East,
Bangalore - 560
011.
Permanent Address : No.9, Bakthavachalam Nagar,
Sathuvachari, Vellore - 632009.
Contact number : Mobile: (0-953*******, (0)
Email ID : acdr10@r.postjobfree.com
Declaration
I declare that the information and facts stated
here in above are true and correct to the best of my knowledge
and belief.
Date: 21/03/2014
D. Sathish Kumar
Place: Bangalore
Signature
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