Design System
Resume:
Curriculum Vitae
Nimit Harkawat
Shakeel Bulding,Arkere Gate
BG Road Email: *************@*****.***
Bangalore 560076 Contact no. :
Summary of Qualifications
> Good understanding of the ASIC and FPGA design flow
> Experience in writing RTL models in Verilog HDL and
Testbenches in SystemVerilog
> Very good knowledge in verification methodologies
> Experience in using industry standard EDA tools for the front-end
design and verification
VLSI Domain Skills
HDLs: Verilog and VHDL
HVL: SystemVerilog and PSL
Verification Methodologies: Coverage Driven Verification
Assertion Based Verification
TB Methodology: UVM
EDA Tool: Modelsim and ISE
Domain: ASIC/FPGA Design Flow, Digital Design
methodologies
Knowledge: RTL Coding, FSM based design, Simulation,
Code Coverage, Functional
Coverage, Synthesis,
Static Timing Analysis, ABV
Professional Qualification
Maven Silicon Certified Advanced VLSI Design and Verification course
from Maven Silicon VLSI Design and Training Center, Bangalore
Year: July 2013
Bachelor of Engineering, Geetanjali Institute of Technical Studies,
Udaipur, Rajasthan Technical University, India
Discipline: Electronics & communication Engineering
Percentage: 65% Year May 2011,
Secondary 74% Year Jan 2005,
Senior Secondary 77.4 % Year Jan 2007
Experience
July 2013 - Present, Maven Silicon, VLSI Design and Training Center
VLSI Projects
Dual Port RAM - verification
HVL: System Verilog
EDA Tools: Modelsim, Questa - Verification Platform and ISE
> Implemented the Dual Port Ram using Verilog HDL independently
> Architected the class based verification environment using system
Verilog
> Verified the RTL module using System Verilog
> Generated functional and code coverage for the RTL verification sign-
off
Router 1x3 - RTL design and Verification
HDL : Verilog
HVL : SystemVerilog
EDA Tools : Modelsim, Questa -- Verification Platform and ISE
Description : The router accepts data packets on a single 8-bit port called
data and routes the packets to one of the three output channels, channel0,
channel1 and channel2.
> Architected the design and described the functionality using Verilog
HDL.
> Architected the class based verification environment using system
Verilog
> Verified the RTL model using SystemVerilog.
> Generated functional and code coverage for the RTL verification sign-
off
> Synthesized the design
GPIO IP Core - Verification
HDL : Verilog
HVL : System verilog
EDA Tools : Modelsim, Questa -- Verification Platform
Description : The GPIO IP Core is user Programmable general purpose 32- bit
input/output controller. Its use is to implement functions that are not
implemented with the dedicated controllers in the system.
.
> Architected the class based verification environment using system
Verilog
> Verified the RTL model using Universal Verification Methodology.
> Generated functional and code coverage for the RTL verification sign-
off
AHB to APB bridge - Design & Verification
HDL : Verilog
HVL : System verilog
EDA Tools : Modelsim, Questa -- Verification Platform and ISE
Description : The AHB to APB bridge is an AHB slave, providing an interface
between the
highspeed AHB and the low-power APB.
Architected the design and described the functionality using Verilog HDL.
Architected the class based verification environment using system Verilog
Verified the RTL model using Universal Verification Methodology.
Generated functional and code coverage for the RTL verification sign-off
Synthesized the design
Basic AMBA Advanced Extensible Interface (AXI4) Protocol Verification
HVL : System Verilog
Methodology : UVM (Universal Verification Methodology)
EDA Tools : Questa - Verification Platform and ISE
Description : The AMBA AXI protocol is targeted at high-performance,
high-frequency system designs and includes a number of features that make
it suitable for a high-speed submicron interconnects. The AXI protocol
includes optional extensions that cover signaling for low-power operation.
> Verified the protocol using Verilog HDL.
> Architected the class based verification environment using system
Verilog and UVM methodology.
> Generated functional and code coverage.
Work Experience
Associate Design Engineer, R&D Dept. Pyrotech
Electronics pvt ltd
Udaipur,Rajasthan
January 2012 - 3 Dec 2012.
> Testing of constant current LED drivers,
> Thermal analysis of LED drivers using Thermal Imaging Camera.
> Fault analysis of LED drivers & finding solution & preventive actions
for the same.
> Modification of LED drivers as per customer requirement.
> Designing & testing of 12 V 1A power supply
References
On Request
Contact this candidate