Process Design

Ming Zhang ***** Crawford St. #*, Fremont, ***** 408-***-****

.

Ph. D in Electronic Materials US Permanent Resident *********@*****.***

OBJECTIVE & HIGHLIGHTS:

Interface, lead technology or product development; demo, improve yield via tests & data analyses

10+ years development experiences under start up, R&D, or production environments, resolving engineering issues;

hand-on, drive or collaborate with cross-functional teams

GaN power device, GaN LED, Engineering Substrate, Si memories, Chalcogenide materials, MEMS Sensors

EDUCATION & EMPLOYMENT:

Device Integration Manager Avogy, Inc. 07/13 ~ 04/14

Sr. Engineer Micron Technology, Inc. 03/04 ~ 06/13

Researcher MRL-UIUC (DOE national facility) 10/03 ~ 02/04

Sr. User Cornell Nanofabrication Facility, Cornell University 12/98 ~ 10/03

Ph. D. Electronic Materials, University of Illinois (UIUC) 05/98 ~ 09/03

M.S./B.S. Thin Films, Materials Science, Tsinghua University 09/91 ~ 05/98

SKILL SET:

Engage with ventures & leadership, integrate & develop technology into existing/new businesses

o Use diverse background applying, analyzing, interpreting a variety of standard theories, concepts, methods

to wide range issues across technical disciplines

o Communicate customer requirements, reconcile with management needs, work from defined system

specifications to determine control architecture

o Identify road-block challenges; design, execute, analyze complex projects; Audit team member’s

experimental & analyses; implement yield improvement solution

o Use fab resources effectively; work with cross-functional groups constructively

Apply industry statistic control & scientific methodology in plan, milestone, risk-management; attain key

deliverables on time

o Design of experiment (DOE), Statistic Process Control (SPC), Reliability; Data Analysis using JMP/JSL;

Device (RRAM, DRAM, NAND, NOR, PCM, LED, MOS, BJT, diode) structure & function, integration,

assembly, etc.

o FEOL, MOL, BEOL integration (5x, 3x, 2x nm nodes), technology road map

o Processes in evaporation (thermal, e-beam, laser), CVD, PVD, ALD, Implant, Diffusion, Spin-cast; Wafer

bonding & layer transfer

o Research background on thin films, metallurgy, thermodynamics, kinetics, electronic materials

Hand-on hardware + software capability

o MEMS sensor from design, fabrication, characterization to application

o Electronic systems: hardware, firmware & software, data acquisition, analysis

o Inline Param, Wafer Probe, LED electrical / optical characterization, reliability

Material Characterization, Failure Analysis

o SEM/EDS, TEM, STEM, AES, XPS, RBS, SRP, SIMS, ICP, FIB, AFM, stress, Rs, Hall

STARTUP EXPERIENCE:

GaN on GaN vertical JFET in lab & wafer fab (2013-14)

Demo device function against design spec: data analysis, pareto correlation, yield improvement

Interface MOCVD, device, process, characterization, operation teams

Resolve road-block challenges, identify & implement inline control

Hand-on critical process (core technology) as needed

Manage traveler, implement conversion

FAB EXPERIENCE:

GaN production fab & reliability lab (2011-13)

Improve yield and fab cost structure for GaN on poly-Al LED business

Manage engineering and production travelers, interface fab logistics implementing conversion

Resolve engineering issues, fight excursion

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Ming Zhang 46711 Crawford St. #2, Fremont, 94539 408-***-****

.

Ph. D in Electronic Materials US Permanent Resident *********@*****.***

LED Reliability Lab operation

Reliability tests: HTOL, WHTOL on device electrical, photometric & radiometric performance

Data Analysis

Technology transfer, integration, development, fab ramp-up (2011)

Lead engineering team deployed to Salem, NH, observe & analyze Amber Wave “lab” processes, improve

& port to new tool sets (Implant, CVD, Diffusion, Assembly, Wet Process, Metrology, RDA) with

100x defect reduction in Boise pilot Fab, with key baseline data defined & collected, logistics via

traveler well controlled, process exploration conducted with no 1st order pareto issue, excursions,

unknown & not resolvable by tool vendor are successfully characterized & fixed, achieving >60%

yield, >150 wfrs/wk in 4 months

New concept from design to implementation (2010)

Innovate Si-Metal-On-Insulator from 3D layer-stacking effort; simulate implant & resistance; separate

material, process & integration challenges for fix; select test vehicles, mask levels & design process

flow & tool sets to demo pillar SMOI diode & vertical MOSFET successfully

Technology set up introducing exotic materials in R&D Fab (2010)

Identify key challenges to be baseline, contamination path & detection method; extract impacted tools

information from Trace Lab database, define TOF-SIMS (new, fast) + VPD (conventional, slow)

method; set up protocol; successfully executed with all excursions captured

Integration (VLSI 5x, 3x, 2x nm nodes) (2008-10)

3D layer-stacked devices: evaluate fundamental Si quality physics from epi over-grow, solid phase epi,

laser melt/re-grow, wafer bonding & SOI layer transfer. Work with design, TCAD, integration &

process team on structure, spec, process flow & cost analysis

Source/Drain – using DRAM test vehicle to evaluate RTP, spike, microwave, laser anneal in dopant

activation in the process flow: Rs, leakage current reduction, Ids boost, Vt impact

Bit-line, metal interconnect road map – simulate liner (diffusion barrier, seed, adhesion layer) & metal

conductor Damascene process resistance trend in technology nodes; correlate Rs data addressing

process related issue like photo / etch on structure short, trench profile / metal fill on void & seam,

CMP / wet clean on leakage, adhesion on electro migration (JMP/JSL analysis); use spacer to shrink

test vehicle for Rs, Rc, defectivity forecast

Process Development (2004-08)

STI – coordinate with Photo, Dry Etch, CVD & Diffusion areas to create various array trench profile to test

HDP, HARP, selective HARP, furnace TEOS, Flow Fill & different densification strategy to minimize

CD imbalance caused structure bending, post CMP wet recess defect; manage external collaborations

(JSR, AMAT, ATMI, Aviza, Kornic, DSG technology, etc.)

Pitch-double pattern transfer – working on CVD, DOE pattern density impacted CD imbalance & stress

related line wiggly issues to enable production

Evaporation, Laser ablation, PVD on exotic materials (Chalcogenide, mix-valence bond oxide)

Capital equipment planning, purchase, facilitation, site acceptance & start-up

Micron’s 1st HARP (CVD) tool (2004); Research cluster tool (evaporation, PVD, PLD) (2010)

LAB EXPERIENCE:

Design and implement an enabling technology in TEM (2003)

Design & make a prototype MEMS TEM holder with 4 electric I/O in confined space

Hand-on sensor fabrication (1998-04)

Design, CAD Layout, Verification, Mask Generation

Photolithography, Dry & Wet Etching, Sputter, Evaporation, CVD, Diffusion, Lift -off on membranes

Transfer technology from CNF to UIUC Micro-Electronic Lab

Hardware + software

Data acquisition, instrument programming using C, Assembly, Labview, GPIB, RS232/485, Modbus

Inline TLM bench tester for production (2013)

Cluster oven system with production recipe and data log (2012)

Custom-built HV & UHV evaporators, anneal & resistance characterization systems, laser –optics bending

plate stress machine (98-03)

ACHIEVEMENT:

3 national & international awards, 2 invited talks, > 20 journal publications, >10 patents, up on request

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