VHDL, Verilog HDL

RESUME

Achan Raghavendra

E mail: ***********.*****@*****.*** Mobile No: 095********

Carrier Objective

Career Objective

Seeking a position to utilize my skills and abilities that offers professional growth while being resourceful,

innovative and flexible.

Personal Skill

Comprehensive problem solving abilities, Willingness to learn, Good team player,

Self motivated.

Academic

PG Diploma in VLSI Design from C DAC ATC, Nagpur.

B.E in Electronics from Dr.Babasaheb Ambedkar Marathwada University, Maharashtra

in 2013 with 63.33%(1st Division).

Diploma in Electronics and Communication from T.B.Girwlkar Polytechnic, Ambajogai, Maharashtra in

2010 with 71.21% (1st Division).

HSC (intermediate) from Yogeshwari Mahavidyalaya, Ambajogai, Maharashtra in 2007

With 48.33% (2nd Division)

SSC from New High School, Parli Vaijanath, Maharashtra in 2005 with 75.20 %( 1st Division).

Technical Skill

FPGA Altera DE2 (cyclone II)

HDL/Programming Languages VHDL, Verilog HDL, C

Development Tool QuartusII 8.1,Xilinx ISE, Tanner T spice

Projects

CDAC Projects:

Title: FPGA Implementation of Median Filter with Sort Hardware Accelerator

Platform: RTL Coding (Verilog/SystemVerilog/VHDL)

Duration: 2 Months

Description: This project is to develop the operative part of a median filter to sort a clearer image by implementing

a systolic architecture sort hardware developed in VHDL. Median filter has good capabilities for reducing a variety

kind of random noise, and causes less ambiguity than linear smoothing filters under same processing size.

Cyclone II Altera DE2 board was used for the implementation.

Title: Comparison of CORDIC and Adaptive CORDIC VLSI architecture

Platform: RTL Coding (Verilog/SystemVerilog/VHDL)

Duration: 1 Month

Description: CORDIC stands for Coordinate Rotation Digital Computer are an iterative algorithm for the calculation

of the rotation of a two dimensional vector, in linear, circular and hyperbolic coordinate systems, using only add

and shift operations. The CORDIC algorithm is used in the evaluation of a wide variety of elementary functions. It

is a simple and elegant method, but it suffers from long latency. The Angle Recoding method is able to reduce the

number of iterations by more than 50 percent.

Title: FPGA Implementation of High speed Vedic multiplier

Platform: RTL Coding (Verilog/SystemVerilog/VHDL)

Duration: 1 Month

Description: Vedic Mathematics is the ancient system of mathematics which has a unique technique of

calculations based on 16 sutras. The high speed 8x8 bit Vedic multiplier architecture which is quite different from

the Conventional method of multiplication like add and shift. Further, the VHDL coding of Urdhva tiryakbhyam

Sutra for 8x8 bits multiplication and their FPGA implementation on Cyclone II Altera DE2 board have been done

and output has been displayed on LEDs of Altera DE2 board.

BE Projects:

Title: Secures Wireless Communication for Industrial Automation and Control

Description: The aim of this project is to monitor and control industrial parameters using wireless technology such

as Zigbee. Zigbee provides proper network topology, and to develop a wireless technology for industries for data

acquisition of parameters like temperature, light, etc.

Hardware : ARM7, Zigbee, Sensors.

Software : Keil uvision.

Personal Information

Date of Birth : 05/01/1991

Father’s Name : Achan Rameshchandra

Gender : Male

Nationality : Indian

Address : B 412, ARK Tower,

Mayurinagar, Miyapur,

Hyderabad 500049,

Andhra Pradesh.

Languages Known : Marathi, Hindi, English and Telugu

I hereby declare that the information given above is true to the best of my Information knowledge belief .

Date: Signature

(A.Raghavendra)

Contact this candidate