M.Tech VLSI Fresher with Skills in Verilog,VHDL,System verilog,UVM,STA

M PRANEETHA

Mobile : 91-855*******

Email : ************@*****.***

OBJECTIVE

To be responsible, committed and reliable in technical as well as

challenging fields that gives scope to enhance my knowledge & skills in the

field of VLSI which can be used for both organizational and personal

growth.

PROFESSIONAL SUMMARY

. Good understanding of the ASIC and FPGA design flow.

. Experience in the area of ASIC and FPGA Design and Verification.

. Good knowledge in Digital design.

. Good experience in RTL Design using VHDL and Verilog HDL.

. Experience in Logic Design and STA.

. Proficient in RTL design, simulation and synthesis using Xilinx ISE.

. Strong testing and debugging skills.

. Experience in developing TB and TB components for block level

verification using system verilog.

. Good understanding of OVM and UVM methodologies.

. Familiar with RMII,I2C,HDLC,SPI,AXI,AHB protocols.

QUALIFICATION

. Certified for "Advanced VLSI Design and Verification course" from

Maven Silicon VLSI Design and Training center,Bangalore.

. M.Tech with specialization in VLSI-SD from Aurora's Technological and

Research Institute, JNTU University in march 2012 with 75.9%.

. B.Tech with specialization in Electronics and Communication

Engineering from MRRITS, JNTU University in 2009 with 68.2%.

. Intermediate with specialization in MPC from Sri venkateshwara Junior

college, Intermediate board in 2005 with 75.6%.

. SSC from Sri Aurobindo High school in 2003 with 83.1%.

TECHNICAL SKILLS

Languages : Verilog HDL,VHDL,System Verilog

EDA Tools : Modelsim,Questasim,Xilinx ISE,Chipscope

analyzer

Methodologies : OVM,UVM

protocols : Ethernet,SPI,I2C,HDLC,UART,AXI,AHB

Worked on : Spartan 3E

Projects Summary:

Freelancer projects

Project #1 : Designed SPI Serial to Parallel Data Converter

HDL : VHDL

Tools : Xilinx ISE

Description:

Designed a core which converts the serial data coming from SPI Master

to parallel and it will convert parallel data coming from peripherals to

serial and send to SPI Master. It will take minimum 32 clock cycles for one

data transfer i.e. 32 bits. It supports data transfer at both edges of

clock.

Responsibilities:

. Implemented logic design and RTL coding.

. Functional verification of system, Synthesis and bit file generation.

. Timing analysis for design and checked timing constraints.

. Done on-chip verification using Xilinx chipscope analyzer.

Project #2 : Reduced Media Independent Interface.

HDL : VHDL

Tools : Xilinx ISE

Description:

This is an Ethernet Protocol used for communication between MAC and

PHY. It is capable of supporting 10Mbps and 100Mbps data Rates. It provides

independent 2 bit wide (di-bit) transmit and receive data paths.

Responsibilities:

. Logic implementation and RTL coding.

. Functional verification and synthesis of design.

Training projects

Project #3 : Design of Inter Integrated Circuit (I2C) Master

HDL : Verilog

Tools : Xilinx ISE

Description:

Inter-Integrated Circuit is a serial bus protocol. It is a two wire

interface through which various system component chips can communicate with

each other and with the rest of system. Generally, a bus master device

initiate a bus transfer between it and a single bus slave and provides the

clock signals.

Master has to read the on board temperature sensor value for every

one minute by using I2C interface.

Responsibilities:

. Implemented logic design and RTL coding.

. Functional verification of system,Synthesis and bit file generation.

. Targeting the design to Spartan 3E FPGA.

Project #4 : Verification of AHB Slave.

HVL : System verilog

Methodology : UVM

Tools : Questasim

Description:

AHB is a new generation of AMBA bus which is intended to address the

requirements of high-performance synthesizable designs. AHB supports the

efficient connection of processors, on-chip memories and off-chip external

memory interfaces with low-power peripheral macrocell functions. AHB is

also specified to ensure ease of use in an efficient design flow using

synthesis and automated test techniques.

It is a high-performance system bus that supports multiple bus

masters and provides high-bandwidth operation.

Responsibilities:

. Built the Test environment and framing of test cases using System

Verilog.

. Architected the class based verification environment using System

Verilog.

. Verified the RTL module using System Verilog.

. Responsible in creating directed and random test cases and for

functional and

code coverage improvement.

Academic project (M.Tech)

Project #5 : FPGA Implementation of Real Time Maximum Likelihood

Space Time Decoder for MIMO

HDL : VHDL

Tools : Modelsim, Xilinx ISE 12.3, Xilinx chipscope

Description:

The project describes the concept, architecture, development and

demonstration of a real time maximum likelihood Alamouti decoder for a

wireless 2-transmit 2-receiver Multiple input and multiple output (MIMO),

which gives the high data rate. It is implemented on Xilinx Spartan 3E

Field programmable gate array.

Responsibilities:

. Implemented logic design and RTL coding for design.

. Done On-chip Verification using chipscope.

. Synthesized the design using Xilinx Spartan 3E and documented the

project.

REFERENCE

Place:

Date:

( Praneetha M )

Contact this candidate