Curriculum Vitae

NAME: Li Cao

TILE: Component Design Engineer

HOME ADDRESS: **** ****** *** **** ****, Ca 94303

CELL PHONE: 916-***-****

EMAIL: acdoi3@r.postjobfree.com

WORK STATUS: USA CITIZEN

OBJECT:

Seeking a challenging position in IC design, analog design, and logic

design

EDUCATION:

M.S. in Electrical & Computer Engineering, 2004

Portland State University, Portland, OR GPA: 3.67/4.00

Major courses:

. Digital Integrated Circuit Design

. Analog Integrated Circuit Design

. Microprocessor System Design

. Computer Architecture

. Introduction to IC Testing

. Communication Systems

. ASIC: Modeling and Synthesis

. Advanced Logic Synthesis

B.S. in Electrical Engineering, 1996

Yanshan University, Qinhuangdao, China GPA: 3.67 /4.00

WORK EXPERIENCE

Xilinx Corporation IC Design Engineer

San Jose, California Jan 2013 - June 2013

. Working on ASIC IO buffer design and simulation. EMIR analysis on

28nm signal and power. Power estimation of power dissipation on

static power and dynamic power. Circuit vs RTL check (LEC check).

Control logic design. Systemverilog coding. Base on RTL to generate

schematic. Modify schematic and layout. Hspice simulation.

Intel Corporation Component Design Engineer

Folsom,California April 2007 - Dec 2012

. Working on Graphic Logic Design and validation - designing control

logic to receive the command from software, designing control logic

between units to control the bit stream flow between units, VC1 decode

and encode design. Writing the random test for MPEG4 based on the

specs with the perl scripts. systemverilog coding, congress test

simulation and validation, design debug, ECO with the logic synthesis

netlist, solve timing issue, insertion, functional coverage and code

coverage, writing C++ for checker and tracker, writing Perl scripts

for generating test basing on specs and tool automation. STA, UVM TLM

modeling.

. Working on Flash Memory Analog Design and validation- input and output

voltage switch buffer design, glitch filter design and mix signals

design and validation.

Hewlett-Packard Hardware Engineer

Vancouver, Washington July 2005 - Dec 2006

. FPGA design. Writing algorithm for DDR test. PCIE and board level

debugging and troubleshooting. Margin test and HALT test. Verification

of power supply design. Writing python code for the MALT test. Board

level processor debug. Developing serial to parallel interface for the

logic control system with Verilog. DFT test pattern generation and san

insertion for the ink control board.

Sciessence Corporation VHDL Engineer

San Jose, California January 2005 - July 2005

. Developing GPIB Controller and AT Attachment/ATA Packet Interface in

VHDL and Verilog. Develop FPGA. Writing the VERILOG for the interface

functions(C Controller, T Talker, L Listener, AH Acceptor Handshake,

SH Source Handshake, DC Device Clear, DT Device Trigger, RL Remote

Local, PP Parallel Poll, TE Talker Extended) and develop FPGA.

Neturity Corporation Hardware Engineer

San Jose, California 2003 - 2004

. Designing the 32parallel CRC. Develop network security device; Verify

and debug firewall/VPN Verilog. I mainly focus develop the algorithm

and write the VERILOG for the 32 parallel CRC. In this company, I

also debug the Verilog, track back the signal and correct the wrong

signal for the firewall/VPN Verilog.

Penguin Software Corporation Hardware Engineer

Beijing China 1998 - 2000

. Developing and designing PCI video card, including PCI bus, FIFO, and

driver.

Beijing Analytical Instrument Hardware Engineer

Corporation

Beijing China 1996 - 1998

. Circuit designs, verification and maintenance of gas chromatograph.

Write the VHDL or Verilog base on the state machine and verify the

signal

Technical Skills

. Strong knowledge about microprocessor and computer architecture

. Solid technical skills on IC design, device, layout, Hspice simulation

and logic design

. Fully understand test challenges associated with current processing

technology; Familiar with DFT design techniques, e.g. Membist, JTAG,

LogicBist, scan insertion, ATPG and test compression.

. Working experience on DFT tools,Synopsys tools(Design/DFT Compiler,

Tetramax

. Windows and UNIX operating system

. Solid understanding of synthesis, hierarchical design, power mesh

design, timing driven layout (TDL), high speed clock tree design and

tree balance, signal integrity, efficient post-layout timing closure

(setup and hold), geometric design rules

. TA700 PCI, PCI-X bus Analyzer.

. Logic Analyzer, DMV and Oscilloscope

. Writing makefile

. Cadence Virtruso design environment (schematic, layout and simulation)

. Hyperlynx design environment (schematic, layout and simulation)

. Synplify Pro 8.4 design environment(schemactic, stateCAD, VHDL,

VERILOG and FPGA)

. Programming experience in Java, C/C++, MATLAB, Perl and Python Chinese

speak, read and write

. Fast learner

Contact this candidate