vlsi project intern using verilog,system verilog and vhdl
Resume:
RESUME
Y.MRUDULA
Sapthagiri colony, Vivekananda nagar,
Kukatpally, Hyderabad, Email: ********@*****.***
Andhra Pradesh, India – 500072 Mobile: +91-809*******
Career Objective
To succeed in an environment of growth and excellence and earn a job which provides
me job satisfaction and self-development and help me achieve personal as well as organization
goals.
Summary of Qualifications
11 months of experience in RTL coding, functional verification, synthesis,Place and
Route netlist and Timing simulation
Good understanding of the ASIC and FPGA design flows
Experience in writing RTL models in Verilog HDL and Test benches in SystemVerilog
Sound knowledge in verification methodologies like OVM
Experience in using industry standard EDA tools for the front-end design and verification
Developed RTL codes for M.tech academic vlsi projects as Project intern at Neoschip
technologies.
VLSI Domain Skills
HDLs: Verilog and VHDL
HVL: System Verilog
Methodologies: OVM
Verification Methods: Coverage Driven and Assertion Based Verification
EDA Tools: ISE, Modelsim and Questasim
Domain: ASIC/FPGA Design Flow, Digital Design
Knowledge: RTL Coding, Simulation, Code & Functional Coverage, Synthesis,
Static Timing Analysis,CMOS
Operating Systems: Linux, Microsoft Windows XP & Later.
Script: Perl
Language: C language
Protocols: UART,AXI master slave interface
PROJECTS
• ALARM CLOCK with a programmable timer, mini project (Maven silicon)
In programmable timer, the output signal is generated by configuring the internal
register. The signal would be generated with set of control registers and algorithm. The project
has counter algorithm to count minutes to make sure 24 hour format. Whenever the Current Time
and Alarm Time are same then sound_alarm signal becomes high. This IP has LCD driver logic
to display on LCD
• Dual Port RAM, mini project (Maven silicon)
This project describes a 64-bit x 8-bit synchronous, true dual-port RAM design
with any combination of independent read or write operations in the same clock cycle in Verilog
HDL. The design unit dynamically switches between read and write operations with the write
enable input of the respective port. Using verification plan, System Verilog test bench for this
code has been developed and verified different test cases attaining good code and functional
coverage.
Video Graphics Adaptor Controller, Main project (Maven silicon)
This project requires a VGA controller to drive a VGA display with 640x480
resolutions and to display the moving geometric objects. Controller has to generate signal
timings one for horizontal sync and the other for vertical sync and coordinates the delivery of
data on each pixel clock(time for 1 pixel information). This project has been synthesized and
simulated using Verilog and verified for coverage analysis.
Lottery based real time arbiter using AXI master slave Interface – RTL Design and
Synthesis.(Neoschip Technologies)
The proposed RB_Lottery algorithm has better performance of bandwidth
guarantees, and has less average latency of bus requests than the Lottery arbitration. Using 4
masters and a single slave of AXI protocol the tickets come from each of masters on which the
slave functions according to arbiter algorithm. For designing, simulating and verifying the bus
arbiters, the hardware models of arbiters are written with Verilog HDL codes first, and then used
the ModelSim EDA tool for HDL functional simulations.
VLSI Architecture of Arithmetic Coder Used in SPIHT set partitioning in
hierarchical tree image compression.(Neoschip Technologies)
In this project Set Partitioning in Hierarchical Trees (SPIHT) algorithm for image
compression is proposed with arithmetic coder thereby it compresses the Discrete Wavelet
Transform decomposed images. The main objective of image compression is to reduce
redundancy of the image data in order to be able to store or transmit data in an efficient form.
The main algorithm for arithmetic coding using breadth first search has been developed using
Verilog HDL and simulated the code.
Professional Qualification & Experience
VLSI intern at Neoschip Technologies, Hyderabad(march 2013-september 2013)
Maven Silicon Certified Advanced VLSI Design and Verification course from Maven
Silicon VLSI Design and Training Center, Bangalore
Trainee at Maven Silicon, VLSI Design and Training Center,Bangalore (Sep 2012 – Jan
2013)
Educational Qualifications
B.Tech in ELECTRONICS & COMMUNICATION -75.75% (2008-2012) Jawaharlal
Nehru Technological University, Hyderabad, Andhra Pradesh.
IPE (MPC) – 93.6% (2006 - 2008) Board of Intermediate Education, Kurnool, Andhra Pradesh.
CBSE – 86% (2005 - 2006) Central Board of Secondary Education, Kurnool, Andhra Pradesh.
Achievements
Best organizer of paper presentations in ILLUMINATI 2011 in our college.
Attended 23rd International conference on VLSI,2012 held in Hyderabad
Attended U2U conference by Mentor Graphics held in Bangalore 2012.
I do here by declare that the information furnished above is true to best of my
knowledge and belief.
Place : Hyderabad
Date : Y.MRUDULA
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