Design Engineer

SUNDEEP B A

Address: Door#***, ward#**, Date of Birth: 19/11/1988

Hotel Raj Complex, Marital status: Single

Kongadiappa college road, Nationality: Indian

Doddaballapur-561203

Karnataka, INDIA. Mobile : +91-889*******

E-mail : *************@*****.***

Profile

A motivated and enthusiastic ASIC/RTL design and Verification Engineer with 1year post graduate

experience(M.Tech 75%). Strong understanding of design methodologies and design issues, having

worked in development of RTL design and verification environments. Seeking a Design/Verification

methodology role with scope for technical challenge, career progression and possibly customer

interaction.

Employment History

03/2013-Present Trainer ASIC verification

SION Semiconductors

Responsible for development of verification IP’s in SystemVerilog environment, which involves layered

testbench designing in SystemVerilog. Responsibilities included UART,I2C, AXI bus interfaces

verification IP’s development. Verification included RTL level simulations, Assertion based verification.

QUESTASIM(Mentor Graphics) and SystemVerilog HDL

Layered test bench development

Score board results

Functional and Code coverage analysis

Tools supported include MODELSIM and QUESTASIM from MentorGraphics

Technical Summary

Advanced

• Verilog- A system level modelling

• SystemVerilog- testbench modelling

• Digital logic design

• C/C++ Programming

• Implementing xilinx FPGA kits and Xilinx tools

Intermediate

• SystemVerilog- UVM Methodology

• Perl Sripting

• JAVA programming

Education/training

2006-2010 B.E Electronics and Communication 64%

Visvesvaraya Technological University

Project: FPGA Implementation of Low Power Parallel Multiplier

Course included Analog Electronics, CMOS VLSI, Fundamentals of HDL, Microprocessor

2010-2012 M.Tech VLSI DESIGN and Embedded Systems 75%

Visvesvaraya Technological University

Project: STM-1 Framer and de-framer generation by interfacing E-3 Frame

Course included CMOS VLSI Design, SoC Design, VLSI Design Verification, Low Power VLSI

Design, Design of VLSI System, CMOS RF Circuit Design

TECHNICAL PROJECTS

•Designof VGA controller

Description: VGA controller interface requiredfor LCD display with resolution 640x480 with a

clock frequency of 25.175MHz and 60 frames per second(FPS) with two synchronization signals

for horizontal and vertical arrays of pixels.

Contributions:

• Developed a RTL model for the vga interface and demonstrated it on the FPGA

Environment:Verilog HDL, Spartan 3 FPGA board

ACADEMIC PROJECTS

• FPGA Implementation of Low Power Parallel Multiplier(B.E)

• STM-1 Framer and de-framer generation by interfacing E-3 Frame(M.Tech)

ACHIEVEMENTS

• Published a Technical Paper in IEEE XPLORE Digital Library in 2012

• State level Hockey player representing Doddaballpurtaluklevel team in 2004.

I hereby declare that the information provided above is true to best of my Knowledge.

Place: Doddaballpur. Sundeep.B.A

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