verilog,vhdl,Basics of System verilog

RESUME

Venu Yerravelly **********@*****.***,

H-no : 10-6,yellareddy +91-852*******.

peta,

Karimnagar, AP.505303.

Career Objective:

Looking forward for a challenging and innovative career as an engineer and

to use my knowledge through challenging job opportunities, further enhance

my skills through constant learning to meet the challenges in the job.

Experience:

Working as a Design Engineer at Data Point Info Solutions, Hyderabad from

November -2012 .

Undergone intensive training in Custom Layout from Institute of Silicon

Systems Pvt Ltd., Hyderabad.

Education:

Bachelor of Technology in Electronics & Communication Engineering from

K.B. R Engg College, JNTU,Hyderabad in the year 2008- 12 with an aggregate

of 81.30% .

Board of Intermediate Education in MPC from Sri Krishnavani Junior

College,Hyderabad in the year 2006-08 with an aggregate of 81.3%.

Board of Secondary Education from Prathidha High School, yellareddy peta

(vi), Karimnagar in the year 2005-06 with an aggregate of 85 %.

Key Skills

Hands on experience on Verilog programming

Exposure to VHDL programming.

Exposure to Basics of System Verilog.

Exposure to Cadence Virtuoso Layout Editor.

Programming Languages

C

PHP

Projects:

A Spurious Power Supression Technique for Multimedia/DSP Applications.

Client : Data Point Info Solutions.

Role : Developer.

Team Size : 2

Technologies : Verilog by using Mentor

Graphics

The design exploration and applications of a spurious-power suppression

technique (SPST) which can dramatically reduce the power dissipation of

combinational VLSI designs for multimedia/DSP purposes.

Responsibilities:

Leadership of entire Project.

Designing and coding.

Design and Implementation of 8-bit Asynchronous Microcontroller.

Client : Data Point Info Solutions.

Role : Developer.

Team Size : 1

Programming languages : Verilog

This project gives the basic microcontroller operation. It consists of 4-

16 decoder, ALU, clock skew, Event dependant, and Gobal clock

Responsibilities:

Leadership of entire Project.

Designing and coding.

VLSI Based Robust Router Architecture.

Client : Data Point Info Solutions.

Role : Developer.

Team Size : 1

Programming languages : Verilog

This project gives the basic operation of router. It consists of header

based router architecture.

Responsibilities:

Leadership of entire Project.

Designing and coding.

Analog Custom Layout.

I had worked with 130nm Technology and 45nm Technology in Institute

of Silicon Systems Pvt Ltd, Hyderabad. I have Complete knowledge to design

in Standard Cells, op- amps, Band gap reference circuits, Digital to Analog

Converters, Phase lock loop(PLL).

Targeted Technology: TSMC 130nm and TSMC 45nm.

Role: Develop layout from Schematic, floor plan, Power management, clean

DRC and LVS

Challenges: Minimum Poly Routing, Matching, Minimum Area.

Academic Projects:

Project Title : "Radio Frequency Based Remote Industrial Appliances

Control System".

Project Type : Mini Project.

This project presents a RF based remote control of industrial appliances.

The appliances can be controlled using RF remote from a distance and it is

been observed and the project is been designed and implemented.

Project Title : "DESIGN AND SIMULATION OF CAN PROTOCAL".

Project Type : Major Project.

Role : project leader

Team Size :4

Language : Vhdl

Tool : Modelsim

Controller Area Network (CAN) is a serial network that was originally

designed for the automotive industry, but has also become a popular bus in

industrial automation as well as other applications. The CAN bus is

primarily used in embedded systems, and as its name implies, is the network

established among microcontrollers. Its robustness, reliability and the

large following from the semiconductor industry are some of the benefits

with CAN.

Extracurricular Activities:

Paper presentation on E-nose in Vathsalya group of institutions and won the

2nd prize.

Participated paper presentations and games in various Engineering

collages like NIT Warangal, Gokaraju Rangaraju

Personal Information :

Father's Name : Gopala Chary Yerravelly

Date of Birth : 25-08-1990

Address : H. No-10-6

Main Road,Yellareddy pet (Mandal),

Kar?mnagar.

Nationality : Indian

Sex : Male

Marital Status : Single

Language Known : English, Telugu, Hindi.

HYDERABAD VENU

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