Engineer Design

Kurt Pleim

******@*****.***

*** ******* ***** (H) 215-***-****

Lansdale, PA 19446 (C) 267-***-****

Summary

ELECTRIAL ENGINEER with extensive experience in ASIC, FPGA, PC Board,

and Project Management seeks to help your company succeed. Product

knowledge spans Cable TV Systems, LAN, WAN, and Internet/Telephony

Systems, and Radar Systems. Some related areas of expertise are:

Static Timing Analysis (STA) and Formal Verification (Equivalence checking)

Verilog and VHDL HDL coding, synthesis and DFT

IP selection and validation

Simulation, verification, timing closure and design audits

Place and Route, DRC and LVS

Hardware and Software Test & Debug

Perl, Tcl, and Unix shell scripting

Mentor Graphics, Cadence, Synopsys, design environments

Software and firmware design and development

Working in a global design team environment

System and Network Administration

Microsemi, Allentown, PA

2013-2014

Sr. Staff Engineer (ASIC design)

. Synthesized and ran static timing analysis on very high speed parallel

processing design for US govt. Contributed towards the development of

radiation hardened flow for FPGA design. Led a design team to achieve

timing closure on a 667Mhz DDR design.

Arris, Horsham, PA

2013-2013

Consulting Engineer (FPGA design)

. Worked with the Digital Return team to develop low cost products which

integrated SerDes, A/D or D/A converters and Xilinx FPGA's. Evaluated

system level problems and resolved by modifying FPGA code and PC board.

Tested the system using spectrum analyzer and oscilloscope.

IBM, Fishkill, NY

2011-2013

Consulting Engineer (ASIC design)

. Primary area of responsibility was physical design (Power planning, Cell

placement, Clock tree insertion, and routing) of 32nm and 22nm DDR3 for

use as IP in customer ASIC designs. Hand routed critical clocks for ultra

low skew (< 1ps). Worked with internal IBM (Chip Bench, Chip Edit,

Einstimer, etc.) and Cadence tools (DRC LVS) to close timing and verify

manufacturability. Integrated digital and analog sections of design to

ensure proper connections and low resistance routes. Provided feedback to

improve RTL design. Performed design reviews and ensured documentation

(CVS) was completed and up to date.

Lattice Semiconductor, Bethlehem, PA

2010-2011

Consulting Engineer (FPGA design)

. Worked with existing team of designers on an internal Serdes PCS design

for FPGA product family. Wrote verilog RTL code and synthesized designs

for optimal performance of area, timing and power. Verified timing closure

using Primetime for STA and ncsim for verilog simulation. Inserted DFT,

and evaluated design for testability coverage. Ran design audits using

Cadence CDC, LEC and Spyglass auditing tools throughout the design

process. Used CVS for version management of code and documentation. Worked

with layout designers to improve constraints, on timing and I/O port

placement.

eSilicon Corporation, Allentown, PA

2001-2009

Lead Engineer (ASIC design)

. Interfaced with customers to understand requirements, wrote RTL code and

synthesized designs for performance. Verified timing closure using Static

Timing Analysis tools, and Verilog or VHDL Simulators. Inserted DFT, and

evaluated design for testability coverage, and first pass silicon success.

Placed and routed designs and completed LVS and DRC verifications.

Managed relationships with IP vendors to ensure completeness, and

timeliness of deliverables. Verified completeness and accuracy of

constraints for Synthesis, STA and physical implementation (Place and

Route). Ran design audits throughout the design process.

AT&T/Lucent/Agere, Allentown, PA 1995-2001

Distinguished Member of Technical Staff (ASIC design)

. Wrote RTL, simulated and integrated the Transmit/Receive section of a

high speed SERDES interface for Lucent's PI-40C chip set which operates

over multi-protocols (Ethernet, SONET and ATM), and at multi-terabit data

rates.

. Verified design performance, and manufacturability of many ASIC designs

through the use of both internal, and third party CAD tools. Interfaced

extensively with customers, and internal support organizations to deliver

on-time first pass silicon for my customers at Cisco Systems, 3com, and

Nortel. Supported customers throughout the entire development process from

package selection through design, simulation, final test and debug.

Designed almost all ASIC's used in Cisco's 10/100 Ethernet switches

through 2001.

Jerrold Communications/General Instruments/Motorola, Hatboro, PA

1993-1995

Senior Engineer (Cable TV Systems)

. Designed simulated and tested an ASIC using verilog HDL to control the

user interface for the DigiCable set top box converter. Breadboarded, and

evaluated the design using Altera and Xilinx FPGA's prior to ASIC tape

out. Interfaced extensively with ASIC manufacturer during the design.

Contributed to the PC board design for this product.

. Worked on the development of embedded firmware for the DigiCable set top

box.

. Installed and administered a local area network of approximately 25

nodes.

. Administered the CAD environment for Cadence, Synopsys, Xilinx, and

Altera tools running on Sun workstations.

Airborne Instruments Laboratories/EATON Corp, Deer Park, NY

1985-1993

Senior Engineer (Military Radar Systems)

Contributed to the technical volume of a proposal and designed a breadboard

to show proof of concept which resulted in a contract award by the US Navy.

. Managed a small team of engineers to complete a schedule critical

project. Completed the project ahead of time, and under budget.

. Wrote application specific software for facilitating automated generation

of netlists, and backplane wiring diagrams.

. Designed a PC board that interfaced an IBM 1750 microprocessor with AIL's

encoder system for the EF-111 aircraft. The design executed 6 concurrent

DMA transfers, and was implemented in 3 Xilinx FPGA's.

. Designed, a 400 MHz GaAs Board for determining chip rate, and slope for a

Saw Channelized Compressive Interferometer.

. Handled system administrator responsibilities for Workstations running

Mentor, and Viewlogic software.

. Awarded secret clearance from the US government.

Education

MSCS Polytechnic University (Now NYU), Brooklyn NY.

BTEE Rochester Institute of Technology, Rochester NY.

AASEE Suffolk Community College, Selden NY.

Contact this candidate