C, C++, VHDL, Verilog, System Verilog, UVM, RTL Design, Verification

Vaisakh Parameswaran

Address: Samgamam, Manjakkad, Shoranur, Kerala-679121

Email: ************@*****.***

Mobile: +91-725*******/+91-773*******

Summary:

Seeking opportunities in VLSI design/verification with an organization of repute.

Technical Skills:

Verilog, System Verilog, VHDL, Xilinx ISE, ModelSim, Questa Sim, Cypress PSoC.

Programming/Scripting languages - C, C++, Perl, UNIX shell scripting

Verification Methodologies: Universal Verification Methodology (UVM)

Education:

Master of Technology in Electronics Design and Technology,

National Institute of Technology, Calicut July 2013

Coursework includes: VLSI System Design, Digital Systems Design, Basics of VLSI, Mixed Signal Circuit

Design, DSP System Design

CGPA: 8.2/10

Bachelor of Technology in Applied Electronics and Instrumentation Engineering July 2007

Rajagiri School of Engineering and Technology (affiliated to Mahatma Gandhi University), Kerala.

Coursework includes: Digital Electronics and Logic Design, Electronics Circuits Lab, Digital I.C Lab,

Microprocessors and Microcontrollers.

Percentage: 76.

Work Experience:

Graduate Technical Intern May 2012 to April 2013

Server Development Group, Intel, Bengaluru

Projects:

1) Emulation Replay Tool:

Designed and developed a pre-silicon validation tool for finding errors in the functioning of a

microcontroller responsible for the power management of Intel servers. The tool reduced the time taken

by the validation team to locate the exact location of bug in the microcontroller firmware during

validation process.

The tool was selected from the team for being presented at Intel Design and Test Technology Conference.

Language used: C++

2) LUT validator:

Developed a Perl program to reduce the validation effort needed for checking the processor

LUT register values which decides the least time consuming path of data flow between the cores in a

multi-core Intel server architecture. Gained exposure to regression testing.

Language used: Perl

Systems Engineer November 2007 to July 2011

Tata Consultancy Services (TCS), Chennai, India

As a part of the Citicards Customer Communications team, I owned, developed and successfully delivered

several projects resulting in changes to the format of the monthly and annual credit card statements sent to

Citibank customers.

Worked on short term (varying from 2-4 months) projects that involved code changes in the billing and

invoice generation section.

Conducted technical teaching sessions for entry level associates familiarizing them with project-

specific functional flows and software applications.

Received bonus from the client for software implementation, being able to engage continually in high

pace activity and for showing above average effectiveness.

Received ‘TCS Gems’ award for successful completion of several projects.

Platform worked on: IBM Mainframes Languages used: COBOL, JCL, DB2, CICS, REXX

Lecturer, Dept. of ECE, NIT Calicut July 2013 to December 2013

Handled the Xilinx FPGA Lab for post-graduate students.

Handled the digital design using VHDL Lab for post-graduate students.

Training:

Functional Verification using Universal Verification Methodology

Topics Include: UVM verification component development, SoC IP verification using UVM, UVC use in SoC

testbench setup

Project:

1) AHB Interconnect Verification using SV & UVM

Description: AHB interconnect has configurable number of master and slave interfaces, with support for all the AHB

protocol features like split, retry, protection, etc. I was responsible for complete verification of AHB interconnect

verification from scratch as part of 3 member team.

Responsibilities:

- Listing down features and creating test plan for these.

- Developing AHB master UVC components, AHB master sequences, AHB slave UVC and slave sequences

- Developing reference model for AHB interconnect

- Testcase coding, verification closure with 100% coverage criteria

1) USB2.0 Core Verification using SV & UVM (Ongoing)

Project Description: USB2.0 core is a configurable device that goes in every USB2.0 based devices acting as an

interface for data communication between host controller and function controller. USB2.0 can be configured for

different device requirements to support isochronous, interrupt, bulk type of devices. .

Responsibilites:

• Testbench architecture definition, Listing down features and creating testplan for these.

• Developing UTMI sequences, UTMI UVC components, function controller interface UVC, Function controller

DMA and interrupts sequences

• Developing reference model for USB2.0 protocol layer

• Testcase coding, verification closure with 100% coverage criteria

Functional Verification and Verification IP Development using System Verilog

Topics include: Functional Verification using System Verilog, Coverage based verification, Constrained Random

verification, Assertion based verification, Verification IP development using System Verilog, development of

Object Oriented Reusable test benches.

Projects:

1) Functional Verification of Memory Controller using System Verilog:

Description: Memory Controller has support for 8 chip selects capable of connecting different memories like

SDRAM, SSRAM, synchronous chip select and asynchronous chip select devices. Memory controller can be

programmed for different burst lengths, refresh requirements, etc. As part of 2 member team we have used

constrained random verification with coverage as verification closure criteria.

Responsibilities:

• Listing down design features, scenarios for verification and creating testplan based on scenarios listed

Defining the testbench architecture and coding of testbench components for transmit & receive interface,

•

BFM, generator, Monitor, function coverage. Also coded reference model, register model and checker.

Coding testcases as per testplan requirements.

•

Setting up Makefile, regression for running testcases

•

Regression debug and using functional & code coverage as verification closing criteria.

•

2) System Verilog based configurable Verification IP development for AXI3.0 protocol

Description: Development of AXI VIP components like BFM, generator, monitor & functional coverage for both

master and slave interface requirements. AXI VIP capable of connecting to both ACTIVE and PASSIVE interface

requirements. AXI VIP validated using Verilog based AXI slave model.

Responsibilities:

• Defining AXI VIP architecture

• Coding AXI VIP for different interface requirements using a configuration class

• Development of AXI slave model for AXI VIP validation

• Developing testcases targeting different AXI features like burst length, burst type, protection, out of order

transaction, overlapped transactions, ID, etc.

3) Functional verification of Ethernet loopback design using System Verilog

Description: Ethernet loopback design has 2 interface, one of receiving Ethernet packets and other for

transmitting packets. The design checks the incoming packets for CRC errors, short packets, long packets, packets

out of sequence, etc. The design transmits back the good packets and drops the bad packets. I was responsible for

developing complete testbench environment to verify the design by generating different types of packet scenarios.

Responsibilities:

• Listing down design features, scenarios for verification and creating testplan based on scenarios listed down

• Defining the testbench architecture and coding of testbench components for transmit & receive interface,

BFM, generator, Monitor, function coverage. Also coded reference model, register model and checker.

• Coding testcases as per testplan requirements.

• Setting up Makefile, regression for running testcases

• Regression debug and using functional & code coverage as verification closing criteria.

Noteworthy course projects:

Projects on Xilinx Spartan 3E FPGA

1) UART interface with Xilinx Spartan 3E FPGA

Designed the UART receiver and transmitter on Xilinx Spartan 3E FPGA to receive the signals

from the keyboard serially, display on the FPGA LCD and transmit it back to the PC HyperTerminal.

Language: Verilog

2 ) VGA display controller using Xilinx Spartan 3E FPGA

Designed program to interface VGA screen to Xilinx Spartan 3E and to vary colour on the

screen and movement of a pixel on the screen.

Language: VHDL

Cook-Toom Algorithm using VHDL

Implemented the Cook-Toom algorithm widely used for large number multiplication in DSP

processors.

Human Presence and Status Information System

Designed, coded and developed an embedded system to detect the information regarding

the presence and busy/available status of persons in rooms of a large building and transmit the same to a

common point to be accessed by visitors to the building.

Resources used: PIC microcontroller, RF 433MHz transmitter-receiver pair

Conducted seminars on ‘HDLs and HVLs’ and ‘Racetrack Memory’

Co-authored the Intel DTTC paper ‘Pcode Emulation Replay Tool’.

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