Design Data

LAXMIKANT BIRADAR

Voice: +91-776******* Profile: VLSI

Design and Verification

Mailto: ***********@*****.***

OBJECTIVE

To learn new thing and apply the acquired experience in the Research -

Oriented field of VLSI.

PROFESSIONA SUMMARY

> Overall 1.3 year experience in VLSI Design and Verification.

> Good understanding of ASIC design flow.

> Experience in designing synthesizable RTL models in Verilog HDL.

> Test bench and test cases development in SystemVerilog.

> Knowledge in verification methodology.

> Experience as in using industry standard EDA tools for front design

and verification.

PROFESSIONAL EXPERIENCE

Current Employer

> Worked for Aadi Semicon Solutions Ltd Bangalore from Jan-2013 to Till

date

Position: Intern

Profile: VLSI Design and Verification

SKILL PROFILE

HDL Verilog

HVL System Verilog, UVM(Intermediate)

EDA Tools Xiilinx ISE 13.2, Questa Sim 6.4,10.1

Verification Coverage Driven Verification

Methodology

Domain Knowledge Digital Design Methodology, RTL Design, FSM

Based Design, simulation, Synthesis, Code

Coverage, Functional Coverage

Operating Systems Windows, Linux

EDUCATION QUALIFICATION

? Bachelor of Engineering in Electronics and communication from

Visweswariah Technological University Belgaum Karnataka India www.vtu.ac.in

with 61% in 2012-June

? Diploma in Electronics and Communication Engineering from Board of

Technical Education Karnataka with 76% in 2009-June

? SSLC from Karnataka Secondary Education Examination Board with 71%

PROJECTS HANDLED AT AADI SEMICON

1. AHB Master

Role : Design and verification

Hdl : Verilog

Hvl : System Verilog

Tools : Xilinx ISE 13.1, Questa Sim 10.1

Description: AHB is a new generation of AMBA bus which is intended to

address the requirements of high-performance synthesizable designs. AMBA

AHB is a new level of bus which sits above the APB and implements the

features required for l high-performance, high clock frequency systems. AHB

master is verified by developing test bench using System Verilog.

Responsibilities:

. Understanding the Functional Specification.

. Creating Architecture and design document for AHB Master.

. Creating verification plan for AHB Master.

. Developing verification environment for AHB Master.

. Involved in developing test Bench components like Generator, Driver,

Monitor and Score Board for verifying AHB Master.

. Involved in running and debugging test cases.

. Involved in code and functional coverage analysis.

2. 1X3 Router

Role : Design and verification

Hdl : Verilog

Hvl : System Verilog

Tools : Xilinx ISE 13.1, Questa Sim 10.1

Description: A router is a device that forwards data in the form of packets

between cooperating routers. The buffering method used here is store and

forward. The store and forward flow mechanism is best because it does not

reserve channels and thus does not lead to idle physical channel. In this

router input buffering mechanism is used. The router accepts data packets

on a single 8-bit port called data and routes the packets to one of the

three output channels, channel0, channel1 and channel2.

Responsibilities:

. Understanding the Functional Specification.

. Creating Architecture and design document for 1X3Router.

. Creating verification plan for 1X3Router.

. Developing verification environment for 1X3Router.

. Involved in developing test Bench components like Generator, Driver,

Monitor and Score Board for verifying 1X3Router.

. Involved in running and debugging test cases.

. Involved in code and functional coverage analysis.

3. DUAL PORT RAM

Role : Design and verification

Hdl : Verilog

Hvl : System Verilog

Tools : Xilinx ISE 13.1, Questa Sim 10.1

Description: Designed Dual Port RAM using Verilog. Dual Port RAM can be

written and read simultaneously. This special type of RAM has two

unidirectional data ports input port for writing data and output port for

reading data. Each port has its own data and address buses. Both reading

and writing of data occurs on rising edge of clock. Dual Port RAM verified

by developing test bench using System Verilog.

Responsibilities:

. Understanding the Functional Specification.

. Creating design document for Dual Port RAM.

. Creating verification plan for Dual Port RAM.

. Developing verification environment for Dual Port RAM.

. Involved in developing test Bench components like Generator, Driver,

Monitor and Score Board for verifying Dual Port RAM.

. Involved in running and debugging test cases.

. Involved in code and functional coverage analysis.

4. Real Time Alarm Clock

Role : Design and verification

Hdl : Verilog

Hvl : System Verilog

Tools : Xilinx ISE 13.1, Questa Sim

Description: Designed Alarm Clock using Verilog. This Clock has Alarm and

Stop watch facilities. Alarm Clock verified by developing test bench using

System Verilog.

Responsibilities:

. Understanding the Functional Specification.

. Creating Architecture and design document for Alarm Clock.

. Creating verification plan for Alarm Clock.

. Developing verification environment for Alarm Clock.

. Involved in developing test Bench components like Generator, Driver,

Monitor and Score Board for verifying Alarm Clock.

. Involved in running and debugging test cases.

. Involved in code and functional coverage analysis.

STRENGTHS

. Good communication skills.

. Leadership qualities and sense of commitment.

. Easily grasp new ideas and implement in meaningful way.

. I'm self-motivated, smart working, highly optimistic, creative and

determined confidence.

PERSONAL INFORMATION

name LAXMIKANT BIRADAR

Father's Name Veeranna Biradar

Contact E-Mail ***********@*****.***

Nationality Indian

Languages Known English, Hindi and Kannada

Passport Valid

Contact Address No19, Basava Nilya, 1st Cross Ganga Road

Paschime County Abbigere Bangalore Karnataka,

Pincode-560090

Contact Number +91-776*******

DECLARATION

I hereby declare that the above written particulars are true to the best of

my knowledge and belief.

Place: Bangalore

Laxmikant Biradar

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