Manager Design

Mo Taghavi

PO. Box. ******, San Jose, Ca, *****-*313, 408-***-****

Email: ********@*****.***

SUMMARY

. Well-rounded CAD / CAE professional with more than 12 years of hands-on

and direct experiences with Cadence Virtuoso Platform (FE /BE), Design

Methodology, PDK development, and Physical designs / Verification.

. Intimate knowledge of Calibre and Hercules Verification tools and

Extraction.

. Working knowledge of the Synopsys tools, flows and methodologies.

. Foundry Interface and Foundry PDK development and support with Tape-in /

Tape-out flows.

. Very Handy on scripting when needed.

. Passion for problem solving and addressing them in early stage of product

development.

. Demonstrated high interpersonal and communication skills, self-motivation

and ability to work well in a team and under pressure.

SKILLS

Extensive knowledge of CADENCE Tools in DFII / Open Access environment,

Schematic Entry (COMPOSER), Layout Design (VIRTUOSO, VIRTUOSO XL and

CAECO), Auto place & Route (VIRTUOSO Custom Placer, VIRTUOSO Custom Router,

Space Base Router (VSR), Encounter, Block, Cell, Silicon and Advanced

Silicon Ensemble), Verification (Calibre, Hercules, Diva, and DRACULA).

Knowledge of Extraction tools (Calibre xRC and Star RC.

Simulation (HSPICE, HSIM and XA, Spectre and Spectre-APS), Logic Simulation

(VERILOG).

Knowledge of DFII SKILL, Unix / Linux, Java, HTML, csh, Perl, Tcl, and C

programming.

Employment

. Kilopass Technology, Jun, 2013-Present.

CAD and Technology / Foundry Interface.

- Installed, customized, and maintained PDK, model file, rule-

decks, technology files, and standard cells library from TSMC,

GF, UMC, IBM, SMIC, and Dongbu in technology range from 110nm to

16nmFF.

- Written and created schematic and layout utilities Skill script

to automate design process.

- Interfaced with foundries to resolve many PDK related issues

(i.e. peclls, design rules, and DRC/LVS/ERC/Extraction).

- Supported and automated Calibre run set with determination of

"switches and environment variables" for the advanced nodes

technology process.

- Supported FE / BE design flow.

- Evaluated Cadence Encounter P&R tool for deep sub-micron

technology.

- Evaluated other P&R tools (i.e. Pulsic Unity tool).

- Supported / installed and maintained EDA tools and licenses.

Exar Corporation.

CAD Senior Staff Engineer, March, 2001-May, 2013.

* Managed all product releases (Tape-Out) to different foundries.

* Installed, customized, and maintained PDK, model file,

ruledecks, technology files, and standard cells library from

TSMC, GF, Tower/Jazz and Dongbu in technology range from 0.35um

to 40nm.

* Supervised all Analog Mixed Signal back-end activities and

Custom Layout.

* Developed custom utility scripts, CDFs, and ROD based Pcells for

design and layout automation using Cadence Virtuoso Platform.

* Interfaced with Foundries like TSMC, Global Foundry,

Tower/Jazz, Dongbu, Silan, and Episil.

* Developed, managed and supported all DRC / LVS / ERC /

Extraction / Fill generation coding and modification for

physical verification using Calibre and Hercules.

* Developed many Cadence SKILL language scripts.

* Developed PDK (Pcells) and support from 0.6um to 40nm

technology.

* Working knowledge of setup triggers and access controls for

design data version control.

* Managed IP usage and interacted with IP venders.

* Working knowledge of different scripts (i.e. Perl, Tcl, Awk, C-

shell, and C).

* Supported all Analog Mixed Signal Front-end, Custom Design

tools, and simulation.

* Supported Custom Layout Automation tools such as VCAR, VSR, etc.

* Managed and Supported ACPD (Analog Custom Physical Design) flow

in Cadence DFII environment.

* Managed, Installed and Supported EDA tools.

* Supported device modeling and technology.

Chartered Semiconductor.

EDA Technical / Account Manager, March, 1999-March, 2001.

Foundry Program Manager, Sept, 1998-March, 1999.

* Successfully Managed EDA accounts for US (southwest region).

* Initiated customer focused team within EDA group.

* Targeted strategic customers for their EDA requirement.

* Offered solution to the fabless customer's design concern

through the EDA program management.

* Prepared market projection / feasibility for Chartered (GF) EDA

offering.

* Prepared / followed-up of multiple simultaneous e-Flash project

schedule.

* Established the regular weekly meeting with the design partner

to discuss the design issues and customer demands.

* Participated in the selected of the library partners for 0.35um

and 0.25um e-Flash program.

* Met the library partners to discuss the required testchip for

CSM 0.35um, 0.25um and 0.18um process.

* Had constant conference-calls with R & D in Singapore for

Process and tape-out related issues.

* Kept track of the schedule and all tape-out issues.

* Strong understanding of engineering program management skills

and detailed engineering issues with ability to develop,

resource, execute and address issues.

* Helped CAD group by writing / modifying DRC/LVS code (Calibre

and Dracula) for 0.35um / 0.25um std-logic process.

Atmel Corporation.

EPROM Design Manager, Apr, 1998-Sept, 1998.

* Worked on 32M (1Mx32) Synchronous High-Speed Flash Memory.

* Completed the schematic entry and specification sheet.

* Completed the simulation run for critical path.

SK Hynix / Mitsubishi Semiconductor America .

Staff Design Memory Engineer, 1993-1998.

* Worked on Merged MPEGII Decoder & DRAM.

* Prepared 0.35u MML DRC / LVS rules and resolved the issues.

* Verified timing by running H-Spice on different component of

MPEGII.

* Leading the interconnection part of 24M DRAM and MPEGII.

* Prepared the documentation for the TESTING the device (MPEG,

DRAM, and CHIP).

* 16M (2-bankx256kx32) SGRAM.

* 4M (256Kx16) SDRAM.

* 16M (1Mx16) SDRAM.

* Top-Down design procedure for the future activities.

* 1M (64Kx16) DRAM with EDO and VDC functions.

* 16M (1Mx16) CDRAM (CACHED DRAM).

* 4M (256Kx16) CDRAM (CACHED DRAM.

* 1M (64Kx16/18) DRAM Low Voltage (3v).

* 1M (64Kx16/18) DRAM.

* 1M (x1) DRAM.

Capabilities

Conducted analysis and applied research.

Developed leadership and communication skills through a basic project

management.

Applied the physical principle and different computer software in

instrument design.

Public relations and team works, with the tremendous customer focus skills.

Education

Georgia Institute of Technology, Atlanta, Georgia.

MS. in Electrical Engineering.

Georgia State University, Atlanta, Georgia.

MS. in Physics.

. Ferdowsi University, Mashad, Iran.

. BS. in Physics.

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