Manager Engineer

R ick Muscavage

**** ****** ****** ****: 610-***-****

Gilbertsville, PA 19525 ****.*********@*****.***

SUMMARY

Experienced Design Engineer and Manager with 25+ years of design and management expertise focusing on

standard product development.

Demonstrates a mastery of all facets of the product development cycle from product definition through

design, implementation, documentation, emulation, test, debug and customer support.

Proven ability to leverage and build proficiency in new technologies.

Drives and collaborates with multi-disciplinary global project teams ensuring successful, on-time delivery

of new products.

Seasoned leadership and organizational skills. Quickly identifies all outstanding tasks, balances priorities,

anticipates problems, and effectively executes.

Proficient at managing resources including all aspects of budget, schedule, tools, and personnel.

Motivated, articulate and personable communicator wit h the ability to work within a team setting as well

as independently.

Consistently strives for innovative approaches to solve problems resulting in 20 issued and pending US

patents.

PROFESSIONAL EXPERIENCE

Microsemi, Allentown, PA (2013 – Present)

Technical Manager of ASIC Development

Founded a new design team to leverage Intel technology for US Government advanced technology development

projects. The initial project required the development of a massive parallel processing high performa nce system

for data center applications.

Expedited the hiring of eight highly specialized industry leading design experts, in support of a stringent

schedule timeline.

Negotiated system specifications and maintained close customer interaction with the USG customer.

Developed a custom fault tolerant interconnect fabric and self-testing diagnostic system that allowed for

processor core defect recovery.

Established a close working relationship with Intel Foundry Services Group resulting in optimized

power consumption and enhanced performance, using 22nm FinFET technology.

Created a new design flow, libraries and tools for radiation hardening circuits independent of process

technology.

LSI/Agere/Lucent/AT&T Bell Laboratories, Allentown, PA (1992 – 2013)

Technical Manager for Axxia Network Processor Development 2012 - 2013

Led a design team in the development of the next generation of a multi-core PowerPC based Axxia Network

Processor for telecom applications.

This 28nm product was a cost reduction from the previous generation that improved performance 20%

and incorporated advanced power management features. The cost savings was 45% for a $380M five-year

program.

Critical contributor supporting the development of the first generation Axxia Network Processor based on the

ARM Cortex-A15.

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R ick Mus cavage Cell: 610-***-****

****.*********@*****.***

LSI/Agere/Lucent/AT&T Bell Laboratories, Allentown, PA (continued)

2004 – 2012

Technical Manager of Media Gateway Development

Led an international design team of 28 engineers in the development of three generations of a scaleable VoIP

SOC platform for media gateway telecom applications.

Negotiated with tier 1 customers (Ericsson, Cisco, and Huawei) to define the system requirements.

Analyzed tradeoffs to finalize the product architecture.

Developed a multi-processor system architecture optimized to meet voice, data, and video performance

targets.

Integrated new system architecture tools into the development flow to combine hardware emulation and

simulation to better analyze and optimize architecture trade-offs.

Managed the development work of engineering teams in China, India, Israel, and the US for the execution

of hardware specification, design, verification, implementation, validation, and test. Coordinated and

tracked project milestone deliveries between engineering departments.

Delivered fully functional first prototypes on schedule for all three-product generations. Leveraged

existing off the shelf IP, new tools and technology to reduce development time 20% and accelerate the

schedule by 3 months.

Developed low power design techniques and tools to deliver a product with the lowest media gateway

power per channel in the industry.

Designed a flexible Adaptive Voltage Scaling (AVS) system to allow customers to achieve lowes t

possible power implementation. Resulted in a minimum 30% power reduction for all tier 1 customers.

Incorporated the Cadence Palladium ICE system into the development flow to allow pre-silicon validation

and software development to accelerate customer production ramp.

Technical Manager of Digital Signal Processor Development 1997 - 2004

Led a design team in the development of multi-core digital signal processors targeted for 2.5G base band

telecommunication infrastructure applications.

Responsible for all aspects of hardware development from specification through production support.

Distinguished Member Technical Staff 1992 - 1997

Lead circuit design engineer for the modem development group in the Digital Signal Processing laboratory.

Worked closely with wireless development group to maximize re-use between product lines.

Innovation and attention to detail resulted in over ten new product prototypes that entered directly into

production. These products helped to secure AT& T’s PC OEM Modem market leadership position.

Member Technical Staff 1992

Product development engineer for Pentium system timing IC’s (ATTDA400) for the catalog products group of

the Digital Bipolar Integrated Circuits Business Unit.

Responsible for determining customer requirements, hardware specification, and design.

General Electric Space Systems Division, Valley Forge, PA (1983 – 1992)

Senior Integrated Circuit Design Engineer

Project leader of VLSI Circuit development for high reliability space environment applications.

Target applications included timing and control, communications, processor subsystems, and high performance

digital signal processing.

Held a U.S. security clearance.

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R ick Mus cavage Cell: 610-***-****

****.*********@*****.***

EDUCATION

Lehigh University, Bethlehem, PA

Masters of Science in Electrical Engineering

Georgia Institute of Technology, Atlanta, GA

Bachelor of Science in Electrical Engineering

AWARDS

LSI Custom Solutions Division Innovation Award, 2011

Bell Laboratries President’s Silver Award Winner, 1998

AT&T Digital Signal Processing Laboratory Recognition Award, 1993.

General Electric Technical Excellence Award, 1988.

PATENTS

“Autonomous Error Detection”, U.S. Patent pending (2/2014)

“MOSFET Aging Effects Monitor”, U.S. Patent pending (4/2012)

“Digital NMOS / PMOS Transistor Mismatch Sensor”, U.S. Patent pending (4/2012)

“Adaptive Voltage Scaling Using a Serial Interface”, U.S. Patent pending (3/2012)

“Integrated Circuit power Grid with Improved Routing Resources and Bypass Capacitance”, U.S. Patent

pending (3/2012)

“Secure electrically programmable fuse and method of operating the same”, U.S. Patent pending (6/2 009)

“Reconfiguration of embedded memory having a multi-level cache”, U.S. Patent pending (1/2009)

“A PCB including multiple chips sharing an off -chip memory, a method of accessing off -chip memory and a

MCM utilizing fewer off-chip memories than chips”, U.S. Patent pending (7/2008)

“Critical path circuit for performance monitoring”, issued January 8, 2013 as U.S. Patent 8,350,589.

“On-chip variation, speed, and power regulator”, issued November 20, 2012 as U.S. Patent 8,315,830.

“System and method for maintaining the security of memory contents and computer architecture employing the

same”, issued August 7, 2012 as U.S. Patent 8,239,663.

“Integrated Circuit Performance Enhancement Using On-Chip Adaptive Voltage Scaling”, issued April 17, 2012

as U.S. Patent 8,161,431.

“Low power dual-voltage sense circuit buffer”, issued April 23, 2002 as U.S. Patent 6,377,086.

“Computer peripheral device having the capability to wake up from a cold state with information stored before

cold power down”, issued August 28, 2001 as U.S. Patent 6,282,666

“Glitch-free bi-phased encoder”, issued February 6, 2001 as U.S. Patent 6,184,807

“Edge signal restoration circuit and method”, issued August 31, 1999 as U.S. Patent 5,945,850

“Controlled transition time driver circuit”, issued September 1, 1998 as U.S. Patent 5,801,558

“Data converter with FIFO”, issued July 15, 1997 as U.S. Patent 5,648,777

“Normalization of apparent propagation delay”, issued September 5, 1995 as U.S. Patent 5,448,193.

“Programmable clock skew adjustment circuit”, issued December 7, 1993 as U.S. Patent 5,268,656.

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