VLSI Design Engineer

CURRICULUM VITAE

Jaya Virwani M-***, Utkarsh Reserve Bank Staff Quarters,

opp collector office, subhashbridge

Electronics and Communication Engineer

Ahmedabad. 3800027

Mo.-099********

E-Mail ID : acd86r@r.postjobfree.com

Career Objective:

Seeking a position to utilize my skills and abilities in the VLSI Design field that offers

professional growth while being resourceful, innovative and flexible.

Technical Skills:

Proficient in RTL Design using Hardware Descriptive Languages

(VHDL,VERILOG).

Worked on Design Tools like Synopsys Design Compiler, Xilinx –ISE,QuartusII.

Hands on experience on Physical Design Tool of Synopsys IC-Compiler.

Have done Functional Simulation using tools like VCS, Modelsim, Active HDL

Comfortable working with Windows NT/2000/XP, Linux(basic) Operating System.

Acadamic Profile:

Degree Universtiy /Board Year % marks

S.S.C (10th) Gujarat Board 2004 74.29

H.S.C (12th) Gujarat Board 2006 66.46

B.E Hemchandracharya North Gujarat 2010 63.85

2014 CGPA

M.E Gujarat Technological University

(expected) (8.51)

Training

Have done Modular Training Program at MSRSAS (M. S. RAMAIAH School of

Advance studies) which includes:-

Reliable Power aware ASICs.

IC Planning and implementation.

Final year M.E. project (pursuing):

Title :- Digital Watermarking using Reconfigurable DWT

Watermarking image will be embedded into original image by decomposing the image

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and reconstructing it using partially reconfigured FDWT and IDWT respectively.

Implementation includes Verilog coding for

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DWT

Fixed point multiplier

Watermarking algorithm for inserting bits by varying wavelet coefficients.

Synthesis will be done using Xilinx ISE

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Physical Design will be done using Plan Ahead.

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Projects undertaken during 1st year Masters:

Title :- Two Stage Pipelined Multiplier

Fixed Point Mathematics.

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Implementation includes

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Booth multiplexer to choose signed or unsigned multiplication.

Wallace Multiplier which includes:

1. CSA tree (Carry Save Adder)

2. CPA (carry propagate Adder

Pipelining is done by adding registers.

Synthesis is done using Synopsys Design Compiler.

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Physical Design is done using IC Compiler.

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Functional Verification and Gate Level simulation are done using Synopsys VCS tool.

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Title :- Designed and Verified Can Controller (Transmitter)

Used with Automation.

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Implementation includes

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CRC Generator Block.

Bit-stuffing (using NRZ encoding)

Functional Verification is done using Synopsys VCS tool.

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Projects undertaken during Training at M.S.R.S.A.S:

Title :- Design and Implementation of Asynchronous FIFO.

HDL Verilog

Synthesis Tool Xilinx ISE 10.1

Simulation Tool Modelsim 6.5.

Description

- FIFO is sequential access memory or buffer formed by arranging the shift registers used

to store the data values.

- Here we have designed fifo using Asynchronous FIFO pointer comparision technique.

- Specifications Includes-

16x16 FIFO memory.

Write clock frequency 250 MHz and Read clock frequency 100MHz.

- Implementation includes RTL coding of FIFO using Verilog HDL and synthesized on

FPGA using XILINX ISE Tool.

- Functionally Simulated using ModelSim Tool.

Title :- Design and implement 8-bit Processor architecture

HDL Verilog

Synthesis Tool Xilinx ISE 10.1, Xilinx ISE 12.3, Synopsys DC, PT for synthesis.

Physical Design Tool IC complier.

- Description

Specifications includes

8-bit data bus.

4-bit address bus.

ALU operations includes and, or, ex-or, not, addition, subtraction, increment,

decrement.

Two 8-bit registers with memory address register.

Implementation includes

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Fetch unit to capture data from databus.

Control and decode unit to decode opcode and to perform operation accordingly.

Execute unit to perform the operation and capture the output data.

Synthesized on FPGA as well as on 65nm tsmc technology (ASIC).

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Academic Project

Final Year Project of B .E :

Title :- AUTOMATION OF COMPACT FILTER USING LOGO SEIMENS PLC.

Programming language :- Functional Block diagram.

PLC used :- Seimens LOGO PLC.

Tool used :- LOGO SOFT COMFORT!

DESCRIPTION:-

This was the project which was designed to benefit the company

(TRUMAC ENGINEERING co.PVT LTD) by using SEIMENS LOGO PLC and LOGO! TD in

place of the existing KSZ4, DEA1, DEB1 and NOM1. By doing this saving of approximately

fifty thousand rupees was achieved.

Achievements:

Participated in a National Level Technical Symposium Xenesis’08 in Robotics.

Participated in a National Level Technical Symposium Prevoyance’08 in Robotics.

Participated in a National Level Technical Symposium Xplode’08 in Robotics.

Participated in a State Level Technical Symposium Search’09 in Model Presentation.

Participated in a ISTE Student Chapter in Poster Presentation.

Personal Profile:

5th March 1989

Date of birth

Gender Female

Marital Status Single

Languages Known English, Hindi, Gujarati, Sindhi

Nationality Indian

Declaration:

I hereby declare that the above -mentioned information is correct up to

my knowledge and I bear the responsibility for the correctness of the above -

mentioned particulars.

Place: Ahmedabad Jaya Virwani

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