VIVIEN CHIRAMANA acd68y@r.postjobfree.com ****

Hovingham Mobile: 210-***-****

San Antonio, TX-78257

OBJECTIVE

Seeking a challenging engineering position in which I will apply broad technical skills and prior project experience, in

ways that further the goals of an electronics design organization.

ACADEMIC DETAILS

• MS in Engineering with- Electrical Engineering - University of Texas at Dallas May – 2014

• BS in Engineering - Electronics and Communication - JNT University Hyderabad, India May – 2012

TECHNICAL SKILLS

Design Tools Primetime, Cadence design suite, Agilent ADS, AWR MWO, HSPICE, Xlinx, PSPICE

EMSimulator Axiem, HFSS, Momentum

s

Languages C, C++, Java, Assembly (MASM), Embedded C, Verilog, VHDL

Scripting Python, Perl, TCL scripting, Unix Shell Scripting

Software MATLAB, LABVIEW, MS-Office

Processors & 8086, X86 Architecture, ARM-7, Atmega 8

Controllers

Operating Systems UNIX, LINUX, Windows 8/7/XP, Sun Solaris

COURSE WORK

Analog IC Design VLSI Computer Architecture Microprocessors

RF IC Design DSP RF System Engineering Power Amplifier Design

SUMMARY

• Extensive course work in RF and Microwave design

• Experience in CMOS Operational Amplifier Design

• In-depth knowledge of Analog Integrated Circuit Design

• Detailed knowledge of design tools such as Synthesis, APR with Encounter, Custom design with Virtuoso,

SPICE

• Hands on experience with Modern Electrical Measurement Equipment including Network Analyzers,

Oscilloscopes and Spectrum Analyzers

PROJECT EXPERIENCE

VLSI

Arithmetic/Logic Unit Jan 2014 – May 2014

• Developed ALU code using Verilog behavioral code

• Constructed library of standard cells (inv, nand2, nor2, xor2, oa221, mux21 and dff) to convert Verilog

behavioral code into netlist

• Automatic placement and routing of design was done using Cadence’s Encounter. Used IBM 130nm CMOS

Technology

Analog IC Design

Fast-Settling, High-Gain Op-Amp Jan 2014 – Apr

2014

• DISO Op-Amp was constructed to be used as a highly linear voltage buffer

• The schematic was tested using Cadence Circuit simulator. Used 0.25um CMOS technology

Computer Architecture

Cache Design Optimization of Alpha 21264 Microprocessor Aug 2013 – Nov

2013

• The Cache parameters were varied for 3 benchmarks of the Alpha microprocessor.

• Simulated the various possible combinations of parameters using PERL script.

RF IC Design

RF System and Front End Design for Mobile Handsets for 4G Wireless Systems Aug 2013 – Oct

2013

• Constructed LTE receiver for 3rd frequency band of spectrum which included designing of LNA, Mixer and

Oscillator

• Tested the circuit simulation of entire receiver chain using Agilent ADS. Used 0.18um CMOS technology

Microprocessor

Simulator for Elastic Ball Collision Jan 2013 – May

2013

• Computational algorithm was implemented in ARM Cortex M4 processor using TI launch-pad.

• GUI was designed using JAVA

Digital Signal Processing

Channel Estimation and Equalization Feb 2013 – Apr 2012

• Developed and implemented MATLAB code that is able to automatically estimate channel response for given

m-sequence of input and output

Power Amplifier Design

Class J Power Amplifier and Harmonic Tuner Jan 2013 – Apr 2013

• Designed and developed Class J power Amplifier to work at GHz range frequencies

• Tested the circuit in Agilent ADS. Used 0.35um CMOS technology

RF System Engineering

Radar Measurements of Snow Avalanches Oct 2012 – Nov 2012

• Proposed and devised FMCW, multi-chirp, 8 receiver channel phased array radar

• Constructed satellite link to receive and transmit data regarding avalanches

• Tested radar and satellite link using AWR MWO

RF Amplifier Design

Single Stage Narrowband Amplifier and 2-Stage Broadband Amplifier Aug 2012– Nov

2012

• Constructed Single stage Narrow Band Amplifier and 2 stage broadband amplifier

• Tested the schematics using AWR MWO. Trans Impedance gain calculation was done using MATLAB

Senior Design Projects

Hand gesture based wheel chair movement control for disabled Dec 2011 – Feb 2012

• Proposed the idea and developed computational algorithm for gesture recognition was implemented in

Atmega 8 MCU

• Fabricated transmitter and receiver parts of working model. Have done final testing of the working model

Improved method to increase AES system speed Jan 2011 – March 2011

• Researched on AES encryption method and developed Verilog code to encrypt data using AES

• Devised a method to improve AES system speed to encrypt data faster

HONORS and ACTIVITIES

• Member of Society of Women Engineers at UT Dallas

• 3rd prize winner in regional Robo Rally competition

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