Systemverilog, UVM

K K SUNDAR RAJAN

Mobile: +91-994**-*****

Email: *********@*****.***

Professional Summary:

. A dynamic and career oriented professional, having 1+ year of

experience in VLSI Design and Verification, possessing excellent

technical and debugging skills

. Having extensive experience in Verilog, Systemverilog, UVM, Perl

Scripting, Processor core design

. Having good knowledge in DDR, TCP/IP, Ethernet, AMBA APB, AHB and AXI

Protocol

Technical competence:

Operating System Windows, Linux

Platforms Modelsim, Questasim,Xilinx, NCSim

HDL Verilog

HVL Systemverilog

Scripting Languages Perl

Protocols/Standards DDR, TCP/IP, Ethernet, APB, AHB, and AXI

Methodology UVM

Work Experience:

(March 2013 to till date): Davinci Nanotech Pvt Ltd, Bangalore as a Member

of Technical Staff(I).

Project 1: Verification of Scheduler Block

Environment: Systemverilog, NCSim

Responsibilities:

. Identifying Test case scenarios

. Implementation of direct and random test cases

. Contributed in the implementation of Test bench components and

environment

. Responsible for test case and regression failure debug

. Responsible for generating coverage report and cover group

implementation

. Extraction of cover point bins and exclusion of unwanted bins

. Analyze and improve the coverage by adding direct tests to cover the

uncovered bins

. Closure with regression units and coverage (code and functional)

Project 2: Verification of NIC Block

Environment: Systemverilog, UVM, NCSim

Responsibilities:

. DTP development

. Implementation of verification component and environment

. Implementation of base sequence, base test, direct and random test

cases.

. Responsible for test case and regression failure debug

. Coverage report generation and cover point bins extraction

. Analyze and improve the coverage by adding direct tests for uncovered

bins

. Closure with regression units and coverage (code and functional)

Project 3: Verification of Tx OLE Block

Environment: Systemverilog, UVM, NCSim

Responsibilities:

. Extraction of Test case scenarios

. Development of base sequence and base test

. Implementation of direct and Random test cases

. Implementation of Scoreboard and Monitor block

. Responsible for test case and regression failure debug

. Closure with regression units

Project 4: Design and Verification of Java Processor

Environment: Verilog, Systemverilog, Questasim, Xilinx, Vertex 5

Responsibilities:

. RTL coding and Logical verification of Decode, Instruction Folding,

Aligner, Ibuffer and Cache Coherence blocks(MESI Protocol).

. Development of verification environment and verification components

(generator, driver, monitor and checker).

. Extraction and implementation of test cases

. Work with the team to fix the bugs

. Net list generation and debug for FPGA bring up

Academic Qualification Details:

. B.E.(Electronics and Communication Engineer) from SACS M.A.V.M.M.

Engineering College, Madurai, Tamilnadu, Anna University in 2012 with

CGPA 7.23

. 12th from Sourashtra Co-Educational Higher Secondary School, Madurai,

Tamilnadu State Board in 2008 with 85.9%

. 10th from Sourashtra Co-Educational Higher Secondary School, Madurai,

Tamilnadu State Board in 2006 with 88.9%

Academic Project Details:

Title : A Secure test wrapper design using Verilog.

Role : Module Analysis, Coding and Implementation

Software : Modelsim 5.5 for simulation, Xilinx 9.2i for synthesis

Description : This paper presents a secure test wrapper(STW) design that is

compatible with the IEEE 1500 standard.STW protects both

internal scan chains and primary inputs and outputs, which may

contain critical information(such as encryption key) during the

system operation.

Co-Curricular Activities:

. Presented a paper on ANTI HIV using NanoRobot in National level

technical symposium and won THIRD prize.

. Actively Participated in workshop on Robotics conducted by Anna

University.

. Presented a mini project on Pre-settable timer using Punched cards in

National level technical symposium.

. Presented a Multimedia Presentation on Imagine the Future in National

level technical symposium.

. Presented a mini project on Coal Mining Safety using ZIGBEE Technology

in the intercollegiate science exhibition.

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