Engineer Electrical
Resume:
IVAN VOYTICKI
Wayne, New Jersey 07470
********@***.***
Summary: Highly skilled Electrical Engineer with a unique combination of system, digital, analog, RF and
project management experience. Can provide rapid solutions in many complex design, development, test,
and integration environments. Adept at the use of hardware and software tools. Inactive secret security
clearance.
EXPERIENCE:
NYC Teaching Fellow: 3/11 – Present: I have been awarded a fellowship to pursue a combined Masters of
Special Education and Mathematics degrees at St. John’s University. In my present position I teach high
school mathematics consisting of algebra, geometry and trigonometry in New York City.
Zetek Corporation, New York, NY 6/08 – 2/10: Led a team of three engineers. We were utilizing an Altera
Cyclone III FPGA to interface an 802.11 ARM-based Wi-Fi module, a ZigBee device, several serial ports,
and walkie-talkie communications systems in the 400 MHz range. The FPGA design and simulation was
done using Verilog HDL in a Quartus II and ModelSim environment. Several different versions of the FPGA
were designed for various testing and calibration of the RF paths as well as the other components of the
system. Other tools used included ORCAD, PADS, and Subversion.
L-3 Communications, Camden, NJ 9/02 - 4/08 Department: INFOSEC Hardware Senior Member of
Engineering Staff - Worked on a Lattice XP non-volatile, reconfigurable FPGA for a ground based
TRANSEC application. Coordinating the work of three engineers to integrate IRIG, IP, processor, memory
self-test, and a cryptographic engine’s interfaces in the FPGA. Utilized Verix Real Intent RTL verification
and clock boundary verification tools. Previously used an Actel fusible link FPGA to interface with the
tracking telemetry and control system for a satellite based application. Have also worked with the Altera
EP1C12 gate arrays for communications and encryption systems. Some of the tools being used include
Lattice’s ISPLever tool set, Actel’s Designer, Summit Technologies Visual VHDL Elite for initial design
capture and functional simulation, Synplicity ProLogic 7.3 for synthesis, Altera's Quartus for place and
routing. and ModelSim for back annotated timing analysis. The Summit Elite tool allows for design capture
to occur in the form of either VHDL code, state diagrams and truth tables as well as logic elements. The
design can also be realized as a combination of hierarchical blocks with VHDL code, state diagrams, or
truth tables within the blocks. CMMI experience includes tailoring the L-3 design flow and presenting
several code reviews. Other process activities include the utilization of DOORS, Rational Clearcase and
Clearquest, RCS, and CVS. Developed a general format and process for reviews for FPGA development
of a legacy system which included PDRs and CDRs.
KEARFOTT GUIDANCE AND NAVIGATION CORPORATION, Wayne, NJ 3/82 to 6/02
Senior Engineering Specialist 10/91 - 6/02 Senior Engineer 3/82 - 9/91 Latest project: Radiation Tolerant
FPGA Design for a satellite based gyro system. Utilized an Actel 32000 gate fusible link FPGA operating
at 48 MHz to provide feedback, control, and timing signals for a two axis mechanical gyro system (TARA
III). The FPGA also provided initialization and operational control for a Mil-Std-1553B Mux interface which
was configured as a remote terminal (RT). Formulated the basic approach/architecture of the design,
supervised schematic capture and VHDL code generation, test set design and fabrication, simulation and
initial debug. Generated design guidelines for the card layout and utilized Innoveda PowerPCB to check
artwork. Used Innoveda Viewlogic for schematic capture, EMACS VHDL editor to generate the VHDL
code, ModelSim to simulate the design, ACTMap to merge the net lists and Designer to place/ route the
design in the FPGA. Utilized logic analyzers, serial bus analyzers, analog scopes, digital storage scopes,
counters, pulse generators and unique FPGA test equipment and programmers to debug, test, and
program the FPGA and the card. Proposals and scheduling: I wrote numerous technical proposals
utilizing MS Word for the narrative and VISIO for the block diagrams. Utilized MS Excel to tabulate costing
estimates for the cost proposals and to tabulate stress factors for card components for reliability analysis. I
used Kidasa software's Milestones program for scheduling
Ivan Voyticki (continued…)
both for proposals and on active jobs.
Digital: Designed a variety of embedded computer interface cards for
inertial measurement and inertial navigation systems. Some of these systems included the A-7 nav
computer update, the B-1 1553 Mux adapter, the B-2 IMU and the improved SAHRS. Interfaces utilized
LSI gate arrays, and a variety of TTL families, Analog to Digital Converters, serial and parallel EEPROMS,
8751, 8086, and T805 microprocessors and other devices. Designed and simulated an ARINC 429 aircraft
serial multiplex bus interface using LSIs Concurrent Modular Design Environment installed in a UNIX
based SUN Sparc workstation. The design was implemented as 6000 gates in a 50,000 gate 0.5 micron
LSI gate array. Analog: Designed a multi-channel resolver/synchro to digital converter utilizing a 400 Hertz
synchronous demodulation technique, sine/cosine ratiometric measurements and interfaced it to both an
auto-dump DMA system and a data-on-demand, programmed I/O (PIO) architecture. Systems: Worked
on B-2 IMUP, AMSS, JSOW, ISAHRS, WCMD, TARA III inertial systems which utilized mechanical tuned
rotor gyros, a variety of ring laser gyros and pendulous type accelerometers as their primary sensors. In
addition to detailed card design, on many of these systems, I participated in concept development both at
the proposal stage and initial system design stage to meet customer requirements, interconnect design,
initial system debug and integration, production testing and troubleshooting. Test Software: Developed C
language test software for a multiprocessor T805 transputer system. The transputers in conjunction with a
30,000 gate 1 micron LSI gate array acquired data and provided control signals for a ring laser gyroscope
(RLG) based inertial measurement system used on the T16 Monolithic Three Axis Ring Laser Gyroscope
for the JSOW FSED program. ISO 9001: Responsible for my departments transition into the ISO 9000
system. Attended company wide meetings regarding policy formulations, trained department members
regarding their responsibilities and in methods to carry out those responsibilities and assisted in retraining
them as policies were changed, as audits approached, or as otherwise required.
EATON CORPORATION/AIL DIVISION, Deer Park, New York 6/73 - 3/82 Intermediate Engineer 7/77 -
3/82 Design Engineer 6/73 - 6/77 Digital: Interfaced exciter/RF Source systems to a PDP-11 type bus.
Unit contained a real time counter for synchronization purposes, an autonomous self-test mode, and
numerous digital to analog interfaces for controlling RF components such as VCOs, switches, attenuators,
etc. Controlled and generated waveforms for various deceptive and wideband jamming techniques. RF
Design: Analyzed RF systems and components for critical parameters such as S/N ratio, intermods,
dynamic range, VSWR, etc. Wrote specifications and supervised out-sourcing for various RF components
including an elaborate DRFM (digital RF memory) produced by two California companies. Responsible for
source inspection, specification negotiations, and acceptance testing. Analog: Designed a suppressed
carrier modulator with a programmable bandwidth control, a ramp generator for the Cobra Dane radar
system, and a programmable attenuator for the B-1 countermeasures system. Systems: Supported
system design, debug, and integration of the RF Sources LRU which consisted of a dozen CCAs on a
wirewrapped multilayer motherboard, unique analog modulation techniques generators, and RF
components all in a oil cooled chassis. In addition, supported a two year round-the-clock debug,
integration, production and field evaluation effort of the seventy box ALQ-161 system of which the RF
Sources were one component. Subsequently supported addition of a DRFM capability for the RF Sources.
Wrote numerous card level and LRU level test procedures, which required a detailed understanding of
each units specifications and how they interfaced with the next higher level assembly in the system.
EDUCATION: City College of New York, B.E.E.
William Paterson University 30 credits at in Computer Sciences and Mathematics,
Pursuing a Masters in Computer Engineering at the New Jersey Institute of Technology
Miscellaneous in-house courses in Navigation and Radar Systems and various
programming languages (C, Pascal, Fortran, etc.)
AFFILIATIONS: Member of the IEEE
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