Engineer Process

Aaron Lewis

Design Component Engineer

Mesa, AZ

**********@*****.*** - 480-***-****

Objective: Parlay 17 years of diverse semiconductor manufacturing and ASIC design experience in a

challenging work environment.

WORK EXPERIENCE

Design Component Engineer

RTL MAS Specs/Val Plan - June 1999 to April 2013

Worked on 11 chip designs, many from beginning thru end and post-end multi-stepping support. Highlights

were: Full chip GLS; unit RTL MAS Specs/Val Plan documentation and reviews; pre and post-silicon bug-

boards; extended post-tapeout silicon lab debug; unit checker; pad_IO/pad_logic RTL unit owner (with

emergency re-layout) and PCIE-PCIX y-bridge whole-project integration; travel for reviews and third party

chip delivery; pad full-chip testing; remote customer-usable DFX wave-debug unit RTL for full-chip; shared

DFX unit ownership, ULT model-build/test bench-env/tests, RTL DFX TAP backdoor transactor; SOC Pad_IO/

Pad_Logic RTL unit owner (with several emergency re-SPEC'ed re-layouts) and T-Spec/ ProjectIO-Spec/ PCB

reviews; Full-chip model building, including top-level RTL and TB edits and power-gating insertion; gigabit

Ethernet AVsync RTL unit owner, RTL, ULT env/TB/tests/GLS, RCOMP (from another group) post-tapeout

debug/ fix/ ECO/ future project fixes; miro-architected RGMII/RMII pads sharing of units; emergency ECR/

ECO fixes; GBE-NonGPIO and JKL unit ownership/integration (extreme time zone challenges and schedule).

Intel

Intel - Chandler, AZ - February 1996 to March 2013

Fab Manufacturing Process Engineer

Intel - January 1997 to May 1999

Worked on two processes in oxide polish (CMP chemical mechanical planarization-polish). Highlights were:

eng. equip owner; multi-site support; multi-travel for system-CopyExactly audits, in-person lines-down at

another fab site, multi-supplier/vendor visits; multi-site yield matching and local-site yield excursion task forces;

multi-site projects; specs and install/qual signoff; tool-down task forces; supplier audits/visits.

Recent Graduate Rotation engineer

Intel - January 1996 to December 1996

finished military processor customer reference PCB with some FPGA; 64-bit u-processor validation; oxide

polish fab engineer.

limited IT support

TeleRobotics/OnmiVision - Knoxville, TN - May 1994 to August 1995

Knoxville, TN: May 1994-Aug. 1995:

Contractor during graduate school. Robot arm support; FPGA design clock-counter; off-site support at 3rd

party board mfg plant; limited IT support.

Co-op Student

Northern Telecom - Research Triangle Park, NC - January 1990 to August 1993

6 sessions over 4 years during undergraduate school: Highlights were: lab support; debug-board creation for

customer ring-detection issue; overtime support for customer debug and leading 2 other co-op students.

Bag-clerk

High-School - July 1986 to May 1993

cart-clerk; overnight stock-clerk; early morning stock-clerk; cardboard-box-crusher bailing

EDUCATION

MSEE

U. of Tennessee

January 1996

BSEE in Electrical Engineering

University of North Carolina - Charlotte - Charlotte, NC

1988 to 1994

ADDITIONAL INFORMATION

Skills: Have passport--willing to temp/perm work outside of U.S. Exposure to Linux/UNIX OS C-shell, gvim,

tkdiff, CVS/tkCVS/Git/DesignSync, FC GLS debug/validation, Verilog, VHDL, ULT tests/TB/env/GLS, Lintra,

Spyglass, CDC, full-chip integration, FPGA, PCB, OrCAD, ViewLogic, Magic mask layout, multi-site, multi-

time zone, multi-travel, unit synthesis, unit formal verification (FV/FEV), FC back-end timing, ECOs, FC model

build/debug, FC FPGA debug/support, silicon debug/validation, multi-stepping support, old-project support,

customer board debug, Fab manufacturing CMP, Windows OS, Word, Excel, PowerPoint, Visio, Outlook,

typing/data-entry, show-me-the-data work/decision making

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