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Design Cover Letter

Location:
India
Salary:
25000
Posted:
May 12, 2014

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Resume:

COVER LETTER

G.Nandakumar - M.E VLSI Design having Bachelors in ECE

Dept.,

Email ID: acd3fa@r.postjobfree.com

Contact No.:087********

Dear Sir/Madam,

I am currently studying M.E., VLSI DESIGN in Anand Institute of Higher

Technology under Anna University Chennai.

I have done a certification course in Design and verification in VLSI

domain -VINCHIP SYSTEMS in Chennai. So i am keenly looking to work in

VLSI based companies.

I wish to grab the valuable opportunity to develop my career in your

Organisation and kindly have a look at enclosed Resume.

My key strength includes self starter, passion to learn new things,

analytical & trouble shooting skills, quick problem solving ability

and flexible to work as a team.

I strongly believe that my positive attitude will allow me to be a

valuable asset to the organization. I would appreciate meeting with

you to share my technical skills.

You can contact me on 087******** or email me:-acd3fa@r.postjobfree.com to

set up an appointment for an interview. Thanks for your time and

consideration.

NANDAKUMAR.G

No.3 rovis graphics,

Kelambakkam (pox)

Mobile: +91-875*******

Kanchipuram (dis), - 603103 e-mail ID:

acd3fa@r.postjobfree.com

Chennai, Tamilnadu

India

CAREER OBJECTIVE

A challenging career that will enable me to exhibit my professional

competency to the zenith and will enable to expose my talent to the max, to

reach the height of success.

EDUCATIONAL PROFILE

DISCIPLINE Master of Engineering. (2012 -

2014)

Very Large Scale

Integrated Circuit-Design-VLSI

ACADEMIC RESULT

COURSE INSTITUTION BOARD/UNIVERSITY PERCENTAGE

M.E Anand institute of Anna university 7.8 CGPA

higher technology

B.E Aarupadaiveedu Vinayaka missions 69

institute of university

technology (AVIT),

Chennai

H.S.C Vallalar.Hr.secondar State board 62.91

y

School, east

kottaiyur

S.S.L.C Vallalar.Hr.secondar State board 76.8

y

School, east

kottaiyur

AREA OF INTEREST:

Digital design

Advanced digital system and design

UNDER GOING TRAINING:

DESIGN AND VERIFICATION IN VLSI Certified Course IN VINCHIP SYSTEM

Chennai.

. RTL design - verilog

. Verification- system verilog

. Layout design- max lab tutorials.

SOFTWARE SKILL SETS:

Operating System: windows 2000, Linux -ubuntu

Programming language: verilog HDL, c++, system verilog for

verification

Tools: Iverilog, Max lab, modelsim, tanner,

systemverilog

PROJECT:

TITLE: PERFORMANCE ANALYSIS OF RC4 STREAM CIPHER IN VLSI

DESCRIPTION: RC4 stream cipher which is used for the data security purpose.

The modern Rc4 stream cipher generates 2 bytes of data key stream in one

per clock cycle. Proposal is to improve the performance of modern RC4

stream cipher. By using hardware pipeline and loop unrolling to generate 2

bytes of data. Multi ported memory and co-processor techniques are to

improve the performance and it also generates more number of key streams in

one per clock cycle.

TITLE: FIRST IN FIRST OUT (FIFO)

DESCRIPTION: FIFO is often used to safely pass data from one clock domain

to another clock domain It is mainly used to safely pass multi-bit data

words from one clock domain. In async fifo, data words are placed into a

fifo buffer memory array control signals in clock domain, and data words

is removed from another port of same fifo buffer memory array control

signals from a second clock domain. In sync fifo the read and write

operation is to be done in same clock domain. Fifo RTL is generated by

verilog after this fifo is verified by using system verilog.

TITLE: ARBITER

DESCRIPTION: an arbiter is like a traffic officer. Who decides which

request may pass through next. An arbiter promptly permits the

corresponding operation, delaying second request until the first action is

completed. When arbiter gets the two requests at once, it decides to

perform like a priority wise. Then decide which request is grant first.

Although the arbiter never grant more then one request at a time. This also

verified by using system verilog.

PERSONAL DETAILS

Name : NANDAKUMAR.G

Father's Name : Govindarajlu.R

Sex : Male

Age : 24 years

Date of Birth : 8th Sep 1989

Nationality : Indian

Compatibility : English, Tamil

DECLARATION

I am a hard working person and having commitment towards the

profession. I do hereby declare that the details furnished above are true

to the best of my knowledge and belief.

Place:

Yours truly,

Date:

(NANDAKUMAR.G)



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