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Project Design

Location:
Bangalore, KA, India
Posted:
May 06, 2014

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Resume:

ABHINAV SONKAR

Mobile - +918*********

E mail - acd0k2@r.postjobfree.com

Address - Flat No-301, Plot No-18, 2nd Cross, Near SGR Dental College,

Marathahalli,

Bangalore, Karnataka - 560037

[pic]

Career Objective

Intend to build a career with leading corporate of hi-tech environment with

committed & dedicated people, which will help me to explore myself fully

and realize my potential.

Work Experience

Presently pursuing as Project Intern with SION SEMICONDUCTOR heaving

responsibilities to create Verification environment for RTL designs.

Project during Inter

- Verification for Ethernet MAC Controller using UVM

The project aims at RTL verification of Ethernet MAC Tx/Rx for

various functional test cases. The verification involves

development of UVM test environment, UVM test components, coverage

and assertions plan and integration of all the above in the

environment. This plan also aims at automated verification by UVM

methodology of this RTL Code for various UVM test cases.

- Created test environment using SystemVerilog for SRAM

Developed SystemVerilog based verification environment including

all possible test cases and check the correctness of the Design

Under Test.

Core Competency

- SystemVerilog.

- UVM, OVM.

- Good understanding of fundamentals of Digital Design.

- Good knowledge of Verilog RTL and VHDL coding.

- Good knowledge of C, C++.

- Implemented VLSI and Embedded projects during PG Diploma and BE.

- Good Exposure to technology by PG Diploma in VLSI and Embedded H/W

Design.

- Having practical experience of EDA tools Xilinx ISE, Altera Quartus

II, QuestaSim.

- Having practical experience with FPGA Boards Vertex-6(Xilinx), DE-

II(Altera).

Project Designed During Academics

FPGA DESIGN FOR DDR3 MEMORY ARBITER

Design "Arbiter" which is capable of allowing two systems to

communicate to same DDR3 memory. This "Arbiter" is designed using

Verilog HDL and validate using Xilinx ISE & implemented on vertex-6

FPGA.

PROTOTYPE OF RISC-SPM MICROPROCESSOR

Designed the architecture of RISC Processor using Verilog HDL and

Verify. Processor includes Registers, Data paths, Control lines and

an ALU with a set of 15 instructions and also designed a test bench to

verify the processor and control unit operation.

MICROCONTROLLER PROGRAMMER

This involves the programming of microcontroller and on the same board

the program can be tested through the provided peripherals it has

motor driving circuit also to test, it can be used as development kit.

200 WATT AUDIO POWER AMPLIFIER

It is an audio amplifier (Class B) which amplifies the low power

signals & gives high power output.

LINE FOLLOWING ROBOT

It follows the path by the using IR sensors and controlled by

8051 microcontroller.

Educational Qualifications

Qualification School/College University/Boar Score YOP

d

PG Diploma (VLSI NIELIT, Calicut, NIELIT, 78% 2013

and Embedded H/w Kerala New Delhi

Design)

B.E. (Electronics & VITS RGPV, Bhopal 66.5% 2011

Communication) Jabalpur (M.P)

Training

- Four weeks of Training from M.P.P.T.C.L, Jabalpur on "Communication

System".

- Four weeks of Training from M.P.P.T.C.L, Jabalpur on "Embedded

System".

- Workshop from Think LABS on "Robotics".

Subject of Interest

- Digital Electronics, Circuit Theory, Communication System.

Personal Strength

- Hardworking & Good team worker

- Detail Oriented.

- Adaptable and a quick learner possess skill to work under pressure.

- Proficiency at grasping new technical concepts quickly and

utilizing it in a productive manner.

- Believe in continuous learning and an innovative approach.

Personal Profile

Date of Birth : August 14th, 1989

Permanent Address : 49, Victoria

Hospital Campus,

Bhartipur Jabalpur, MP-482002



Contact this candidate