Project Design Engineer

MOOLI MADHUSUDHAN REDDY

Mail id:********@*****.***

cont.no.:+91-720*******

OBJECTIVE

To obtain an Entry level Physical Design Engineer position that will allow me to utilize my

skills and has potential for growth.

PROFESSIONAL TRAINING

Undergoing training in VLSI Physical Design on Cadence Tools from Institute of Silicon

Systems Pvt. Ltd, Hyderabad since September, 2013.

Course outline

VLSI Fundamentals, CMOS Basics, Digital Design, Floor Planning, Power Planning,

Placement and Routing, clock tree synthesis, static timing analysis, cross talk analysis, IR Drop

Analysis and Physical Verification.

TOOLS

Experience in physical design of 130nm and 90nm technologies using Cadence tools

Cadence SOC Encounter – Floor Planning, Place & Route, and clock tree synthesis

Encounter Timing System – Static Timing Analysis and Crosstalk Analysis

RTL Compiler- Logic Synthesis

Assura – Physical Verification

EDUCATION

Aggregate Year of passing Institute Course

2013

68.88 Mallareddy Eng. College(HYD) B.Tech (ECE)

2009

67.86 LOYOLA POLTECHNIC DIPLOMA (ECE)

COLLEGE,(Pulivendula)

85.45 2006 Nalanda High School,( Pulivendula) S.S.C

PROJECTS

Physical Design

Project 1: PCI_DATA (top level)

Objective : Timing driven layout

Tools : SOC Encounter

128,961 / 1,572,915 um2

Gate count / Area :

Macros / STD Cells : 12 / 24,450

No. of Clocks : 4

Frequency : 149.9 MHz

Utilization : 52.1 %

Technology / Layers : TSMC 0.18 microns / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing

Analysis, CTS, Detail Routing. To achieve 0 % congestion at trial route stage.

Project 2: (block level)

Objective : To observe the usage of metal layers

Tools : SOC Encounter

7,701 / 76,856 um2

Gate count / Area :

STD Cells : 2477

No. of Clocks : 3

Frequency : 333 MHz

Utilization : 70.1 %

Technology / Layers : UMC 0.18 microns / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing

Analysis, CTS, Detail Routing. To observe the relation between core utilization, wire length

and number of metal layers.

Project 3: SPECTRUM (Block level)

Objective : Timing Driven Layout

Tools : SOC Encounter, QRC, ETS

296,296 / 1,508,801.9 um2

Gate count / Area :

Macros / STD Cells : 12 / 25195

No. of Clocks : 17

Frequency : 200 MHz

Utilization : 87.3 %

Technology / Layers : TSMC 0.13 microns / 5 Metal Layers

Role: To perform audit checks, Floor Plan, Power Plan, Placement, IPO, Trial Route, Timing

Analysis, CTS, Detail Routing, RC extract, STA.

Logic synthesis

Project 1 : An 8-bit synchronous counter with asynchronous reset.

Clocks / Frequency : 2/200MHz

Role: Generated Constraint file, TCL file and Performed Wire load and Zero Wire load

model.

Project 2 : A 256-bit counter

Role: To find the frequency of operation of the counter and generate the constraints file, TCL

script and close timing by performing wire load and Zero wire load model.

Layout

Tools : Virtuoso

Design : Basic gates

Role: Designed Layouts for Inverter, Nand, Nor, And, Or gates and Latch.

Academic Projects

An Improved VLSI Architecture for DSSS using QPSK modulation techniques in 4G Digital

Communication during period JAN-MARCH 2012,

• Scope of the project:

The scope of the project a new approach to design VLSI architecture for DSSS is

proposed and implemented. We aimed towards designing a low power and low complexity

architecture and provide network security.

• Tools used: Xilinx,Matlab,Cadence Virtuoso schematic editor.

Personal Strengths

Can handle situations in a way that will not only please the management but also be fair to the

working team.

Hard working nature and loves what I do.

Leadership qualities and at the same time believing in team work.

Self motivation.

Technical Exposure

Programming Languages : Verilog HDL

●

Frontend Synthesis Tools : Cadence RTL Compiler, Xilinx XST.

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Backend Synthesis Tools : Cadence SOC Encounter, Cadence ETS, Cadence Virtuoso

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Scripting Languages : TCL

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INTERESTS:

Learning new Technologies and computer related stuff.

Actively participating in ELECTRONICS discussion forums online.

Playing Table tennis, listening music.

Personal Profile:

Father’s Name : M.Maheswar Reddy

Mother’s Name : M.Laxmi jyothi

Sex : Male

Date of Birth : 20.05.1991

Nationality : Indian

Marital Status : Single

Languages Known : English, Telugu.

Hobbies : Solving puzzles, Playing chess & Gardening.

Permanent address : D.No : 5-1-56,Bremhanapalli,Pulivendula-516390,

Cuddapha Dist,A.P.

Declaration:

I hereby declare that the above mentioned information is correct to the best of my knowledge.

Date: Yours Sincerely,

Place: Hyderabad. (M.Madhusudhan Reddy)

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