Engineer Design
Resume:
Pankaj Ahirwar
Senior Engineer, Marvell Semiconductors
Boise, ID, 83713
******.*******@*****.***
Education 2013
Ph.D. (Electrical Engineering), University of New Mexico, NM,
USA
2005
B. S. (Electrical Engineering), Indian Institute of
Technology (IIT), Roorkee,
Seven plus years of experience in semiconductor device design,
Experience manufacturing and characterization, which has included preparing a
patent application, writing proposals to various funding agencies
and management responsibilities.
Representative Circuits, Analog design, digital design, semiconductor lasers, led,
Arts display technology, printer solutions, epitaxy, processing, FM,
wLAN, GPS, DDR3/4, USB 2/3, PDN, SI FEM, 3D field solvers,
PCB/Package Design and computer hardware/software.
. Marvell Semiconductors, Boise ID (June 2013-Current)
. Senior Engineer, Signal Integrity and Hardware Design
o Perform signal integrity analysis for silicon IO buffer, package and
board designs. Solve signal integrity problems and provide solutions
and trade-offs, high-speed I/O design, simulation (hspice, Sigrity),
DDR3/4PHY and package modeling.
o PCB/Package reviews for good Signal/Power Integrity of Designs.
o Extraction tools (Sigrity, Hyperlynx, Ansoft HFSS, Q3D etc.)
o Generate and validate models for use in signal integrity simulations.
The models include package, via, trace, cable, connector, etc.
o High Speed interfaces integration (USB 2/3, DDR3/4, PCI-e and SATA)
o Board/Package Design (Cadence Allegro)
Skills
. Device Physics and Semiconductor Physics
o Good understanding of Device Physics (JFET, MOSFET, Schottky Diodes,
PIN Diodes, BJT, Lasers and LEDs)
o Good understanding of Circuit Design and analysis (Analog [SPICE,
Tanner], Digital [Cadence, Synopsis] and RF Design [Agilent ADS]).
o Good understanding of Semiconductor (III-V) device Fabrication and
Characterization.
. Signal/Power Integrity
o Good understanding of S-parameters, smith charts, system causality and
passivity analysis.
o Eye-diagram analysis using HPSPICE and wave viewer (Sandwork)
o Familiar with using VNA, TDR.
o Full 3D extraction tools (Sigrity Suite: Power SI, Broadband Spice),
Board extraction (Sigrity, hyperlynx), Ansoft HFSS and Q3D
o PDN analysis on package/PCB designs of Printer ASIC chips at Marvell
Semiconductors
March 2008 -June 2008, Freescale Semiconductors
. Designation: Design Engineer II (Physical Design)
. Domain of work: Evaluation and deployment of statistical timing analysis
(SSTA) and synthesis tools for 45/32nm designs.
. Role: logical synthesis, timing closure, power optimization, place and
route.
Aug 2006 - March 2008, Texas Instruments
. Designation: Design Engineer I (Physical Design)
. Domain of work: Design, Timing analysis, Synthesis and Power optimization
of sub-chips.
. Role: logical synthesis, timing closure, power optimization, place and
route.
July 2005 - July 2006, CSC
. Designation: Software Engineer
. Domain of work: Design and development of Business Objects (Finance and
Insurance).
Education:
. Aug 2008-May 2013, The University of New Mexico, Albuquerque, NM, USA
Degree: PhD
Major: Electrical Engineering
GPA: 3.84/4.0
. 2001- 2005 Indian Institute of Technology Roorkee (IIT Roorkee) -
Roorkee, India
Degree: Bachelor of Technology
Major: Electronics & Communication Engineering
CGPA: 7.44 (on a scale of 10)
Computer Skills:
. EDA Tools: Synopsys (Primetime, Design compiler), Cadence (encounter),
Magma (blast fusion), Tanner, SPICE, Agilent ADS, HSPICE, Cadence
Allegro, Power SI, Broadband SPICE, Q3D extractor, Ansoft HFSS.
. Proficiency in tool scripting languages like Tcl/Tk, Perl, T-Spice.
Contact this candidate