ASIC Verification Engineer 2+ years experience

Resume

PRAVIN W

***, *** ******, ******** *****

Electronic city - 560 100

Phone No: 974**-*****

***********@*****.***

Alternate : 88848

23800

CAREER OBJECTIVE

Aspiring for career enriching assignments in ASIC/SOC

verification with an organization of high repute

PROFESSIONAL SKILLS

. Experience in SOC Verification

. Expertise in Full chip and Unit level debug

. Good Knowledge in ASIC verification flow

. Experience in creation of test cases and debugging test and RTL issues

. Ability in creation of verification environments using Verilog, System

Verilog, UVM, OVM

. Expertise in perl scripting

. Experience in Emulation

. Knowledge in Hardware graphics - 3D

. Experience in module level verification

. Knowledge in communication protocols AHB, APB

SKILL SET

Operating Systems Linux, Windows

Languages Verilog, System Verilog, VHDL,

C

EDA Tools VCS, Xilinx, Modelsim, Orcad

Scripting Perl

PROFESSIONAL EXPERIENCE

Infosys Limited( 2011 October - Present )

Project 4

Client : Intel Corporation

Project: GT - BROXTON Graphics

Duration: October 2013 - Present

Team Size : 10

Roles and Responsibilities:

. Register Test's Development and Debug

. Testlib ownership for waivers

. Developed feature based test cases

. Root cause checker issues

. Involved in GT validation

. Debugged different flavours of failure like Hang, Memory difference,

Compile failure, Crash and Run limit issue

. Ownership of Page fault, a special feature in Testing.

Project 3

Client : Intel Corporation

Project: GT - BROADWELL Graphics

Duration: July 2012 - September 2013

Team Size : 5

Roles and Responsibilities:

. Involved in GT validation - Debug, Bug filing, tracking upto closure

. Debugged different flavours of failure like Hang, Memory difference,

Compile failure, Crash and Run limit issue

. Automated time consuming activities using scripting

. Regression activities

. Owned Software Stress, a special feature in Testing. Involved in

writing and modifying existing Test cases

. Interaction with client on day to day basis to understand new

requirement and map the deliverables

Project 2

Organisation : Indian Space Research Organisation

Project : Design of IEEE 754 Compliant Floating Point Unit

Duration : Nov 2010 - March 2011

Team Size : 1

Roles and Responsibilities:

. Involved in selection of best architecture for adder and multiplier

. Analyzed the performance of various types of adders and multipliers

and implemented the most efficient architecture based area, speed and

power consumption

. Developed test cases and scenarios for the entire unit

. Verification using Verilog test bench

. Verified the compliance with IEEE 754 Standard

. Regular status update and submission of Final report to Avionic

division in ISRO

Project 1

Organisation : Satyam computer services limited

Project: Interface Logic for Air-craft Recroding Unit

Duration : Dec 2008 - Feb 2009

Team Size : 2

Roles and Responsibilities:

. Involved in understanding the CAN and ARINC-429 Protocols

. Developed Interface logic for Processor, Memory and CAN, ARINC Modules

. Developed test cases for provided scenarios

. Coding and verification in VHDL and C

. Regular Staus update and presentation of final report to Embedded

division in Satyam Computer services limited

EDUCATION

Examination passed University Month / Year % or CGPA

Obtained

M.E-VLSI Design Anna university June 2011 82.2%

B.E.-ECE Anna University April 2009 76.67%

HSC TN - State Board March 2005 87.67%

SSLC TN - Matriculation March 2003 85.73%

PERSONAL DETAILS

Father's Name Mr. C.Wilfred Thamby Raja

Sex Male

Date of Birth 10 - 06 - 1987

Nationality Indian

Languages Known Tamil,English,Hindi

Phone Number +91-974**-***** / 888-***-****

Permanent Address 580,2nd cross street,nesamonynagar,

Nagercoil-629001

I do hereby declare that all the

above said details are true

and correct to the best of my knowledge.

Date : 25/01/2014

Place: Bangalore (Pravin W)

Contact this candidate