Engineer Project

ANJALI PRABHAKARAN

(Mob) : 094******** (primary)

Email id: accnhp@r.postjobfree.com

OBJECTIVE

To gain employment with a company or institution that offers me a

consistently positive atmosphere to learn new technologies and implement

them for the betterment of the organization.

EDUCATIONAL DETAILS

MTech( VLSI Design & CMR Institute Of 77.83% Jul-2011

Embedded System) Technology

BE( E & C ) Atria Institute of 70.64% Jul-2008

Technology

PUC National Junior College 77.89% May-2004

CBSE CMR Jnanadhara Trust 76.80% May-2002

School

TECHNICAL SKILLS

Operating Systems Windows 2000/XP

Technical skills C, AutoCad

Software Packages MS-Office

Assembly Level Language 8086, 8085, Keil

Hardware Languages known Verilog, System Verilog

Electronic Design Packages ModelSim, Xilinx ISE, QuestaSim

Familiar Protocols AMBA AHB

Nov 2012-June 2013

Completed a course on VLSI Design & Verification in Sandeepani School of

VLSI Design, Bangalore. I have also worked on Xilinx Simulator.

PROFESSIONAL EXPERIENCE:

Oct 2013 to PRESENT - Working at STelematics as a System Developer

Engineer(R & D Firm).

Project: Image Processing - Designing a system for capturing an image and

process it using FPGA.

Role: Decided which board and which sensor to use. I' am also designing the

entire system for this application which includes the interface of the

system, the clock frequencies required, the delay and the amount of memory

required in the FPGA to store the image and process it.

Board used: Zynq 7045

November 2008- September 2009

Engineer trainee: MECON Ltd. I have worked as an Engineer Trainee in MECON

Ltd (in Communication department). I have worked on all these projects

using AutoCad.

Some of the Projects that I worked on:

. I had to find locations to place the fire protection system in the

Bailadila Iron Ore plant at the NMDC(National Mineral Development

Corporation)

. I had to set up telephone and LAN connections in Kumaraswamy Iron Ore

plant for NMDC.

ACADEMIC PROJECTS

Project Title: SRAM Controller

Software Tools: ModelSim, ISE, QuestaSim

Programming language used Verilog

Brief Description: The S-RAM controller is used to interface four

synchronous requestors with the "IS61LV25616", a 256K * 16 bit asynchronous

static ram memory device. The controller will get the inputs (data,

address) and requests (read and write requests) from the requestor and

grant memory access based on the bus availability.

Role: I have verified the arbiter block by writing a linear testbench, and

also checked the code coverage using QuestaSim. I also wrote the verilog

code for the control block.

MTech 4th Semester Project

Project Title: Realization of AMBA AHB Master & Slave

Programming language used Verilog

Brief Description: With the latest advancement in semiconductor technology

the number of transistors on a chip has exponentially increased which has

increased design complexity but with requirement for less time to market

and low cost. The design reuse is possible only if the cores are used in

plug and play fashion, thus creating demand for widely accepted bus

architectures like the AMBA (Advance Microcontroller Bus Architecture)

developed by ARM.

Role: I have written the verilog code for the AMBA AHB (Advanced High

performance Bus) Master and AMBA AHB slave and interfaced them. I also

demonstrated the working by simulating it on Modelsim.

BE 8th semester project

Project Title: Anti collision systems for trains using GSM

Microcontroller used AT89C51

Programming language used Embedded C

Brief Description: This system can be used in railways to avoid accidents.

There can be two types of accidents of trains; (i) collision if there is

another train in the same track or (ii) if there is a discontinuity in the

track itself leading to derailing of the train. To prevent such accidents

we developed a device that can detect the presence of another train or a

discontinuity in the track. It also sends a warning to the drivers of both

trains as well as to the stations master. GSM is used to send warning

messages to the two stations between which the train is running.

ACHIEVEMENTS:

. Actively participated and excelled in Debate, Dance and Sports

competitions

. Obtained an ISCT certification on computer fundamentals and concepts

of internet

. Represented AIT at the VTU Technology Exhibition

DECLARATION

I hereby declare that the information furnished above is true to the best

of my knowledge.

Date: 14-January- 2014

Place: Bangalore

(Anjali. P)

Contact this candidate