Design Engineer

DHAVALKUMAR SHAMBHUNATH SHUKLA

*,********** *******,*********,***** Buzarg, Godhra 389001

Contact: +91-966*******; Email: ******.******.**@*****.***

VLSI DESIGN ENGINEER

I want to contribute my educational and technical expertise in position with growing and dynamic firm, which

helps in development of whole organization and society as well personal for moving toward better shape of

country’s future.

WORK EXPERIENCE

• Working as an Assistant Professor at Birla Vishwakarma Mahavidhyalaya Engineering College from Jul 2011 to

June 2012.

SUMMARY OF SKILLS

• Qualified M.Tech (VLSI Design) from Nirma University of Science & Technology, Ahmadabad backed by B.E

(Electronics and Communication); determined to carve a successful career in the industry.

• Possess knowledge of Analog & Mix Signal VLSI Design, CMOS Digital IC Design, IC Fabrication

Technology, High Speed Low Power VLSI Design, HDL Based Design, Testing & Verification.

• Understanding of all aspects governing operational activities & up to date knowledge of latest technological

advancements, regulations/ guidelines and statutory compliances in the industry.

• Completed projects “Design, Characterization & Simulation of Advanced Current Mirror using 0.35 µm

CMOS Technology”, “Noise & Distortion Analysis in Current Mode Operational Amplifier”, " Design,

Characterization & Simulation of Schmitt Trigger in 0.35 µm CMOS Technology ”, "Regulated Power Supply

System", “LDR Based Binary Counter”.

• Outstanding communication skills, verbal as well as written coupled with good presentation skills. Self motivated

and goal oriented with a high degree of flexibility, creativity, resourcefulness, commitment and optimism.

Technical Skills

Hardware Languages : VHDL, Verilog

Synthesis Tool : Leonardo Spectrum S

Waveform Simulator Tool : Modelsim, Xilinx ISE Simulator

EDA Testing Tool : DFT Adviser, Fast Scan/Flex test

Assembly Languages : 8085, 8086, 8051

Software Languages : C Programming

Operating System : Windows, Linux

Front End Tool : Xilinx ISE 9.2i, Quartus II 8.1

Back End Tool : Eldo Spice, Design Architect and IC Station(Mantor

Graphics), Tanner Tool (wintsp32, S Edit, L Edit),

Microwind

Other : Keil Microvision, MATLAB, OrCad, Multisim

EDUCATIONAL CREDENTIALS

M.Tech (VLSI Design), 2011

Nirma University of Science & Technology, Ahmadabad; CPI 7.94(I Distinction)

Bachelor of Engineering (Electronics & Communication), 2009

Government Engineering College, Dahod, Gujarat University; 66.55%(I Distinction)

Intermediate

Bright English Medium School, Vadodara GSHSEB, Gandhinagar ; 67.77%

Matriculation

Nootan High School, Godhra, GSEB, Gandhinagar; 84.14%

Projects Undertaken

• Design, Characterization & Simulation of Advanced Current Mirror using 0.35µm CMOS Technology

• Noise & Distortion Analysis in Current Mode Operational Amplifier

• Design, Characterization & Simulation of Schmitt Trigger in 0.35µm CMOS Technology

• Regulated Power Supply System

• LDR Based Binary Counter

Industrial Visits

• Central Electronics Engineering Research Institute(CEERI),Pilani,Rajasthan

• Central Scientific Instruments Organization(CSIO),Chandigarh

• Semiconductor Laboratory, Chandigarhs

• Indian Space Research Organization (ISRO), Ahmedabad

• Doordarshan & All India Radio Station, Ahmedabad

Seminars Presented

• Types of Current Mirror and its implementation in Analog & Mix VLSI Circuit Design

• Technology and Design Challenges in Low Power & High Performance Digital Signal Processing

Paper Publication

• Design and development of self biased cascode current mirror circuit with its implementation using TSMC0.35 µm

technology” IJECT, VOL.2, ISSUE.2, June, 2011

• Design, characterization and simulation of Schmitt Trigger using 0.35μm technology, ICISET 2011

• Comparative study of low power CMOS Class A voltage followers, KITE 2011

• Comparative study and design of wide swing cascode current mirror using TSMC 0.35 µm CMOS technology,

KITE 2011

Workshop Attended

• Exercised with Back End design tool like Eldo Spice(Spice Simulator tool), Design Architect(Circuit Design)

and IC Station (Circuit Layout Design).

• Attended workshop on Synopsys Tool.

• Exercised with Synthesis tool (Leonardo Spectrum) for synthesis purpose using of verilog (.v) file.

Synthesized verilog netlist was scanned by full scan insertion using DFT Advisor(Scan tool flow).Fast Scan/Flex

test was used to generate test vector and test fault coverage (Scan & ATPG tool flow).

• Attended short term training program (STTP) on Low Power VLSI Design.

• Attended workshop of H/W Verification Tool, i.e. Emulator (Ze Bu).

.

Academic Accolade

• Qualified GATE 2009 with 89.51 percentile organized by IIT, Rourkee.

• We have successfully organized the workshop for our M.Tech VLSI junior batch as well as for the M.Tech

Communication batch during 4th Semester of my post graduation to demonstrate the functioning of Mentor Graphics

Tool, which consists Back End Design Tool like Eldo Spice for Spice Simulation, Design Architect for Circuit Design

and IC Station for Circuit Layout Design.

• Nominated as an expert lecturer on how to make a project report using the LaTex software platform during my job

as Assistant Professor in BVM Engineering College.

• Got 1st Rank for Best Teacher in Teacher’s Day during School period of 8th, 9th and 10thstd.

• Selected Report on “AIDS AN ENEMY OF THE SOCIETY” at National Level during 11thstd.

Date of Birth: 15th December 1986

Marital Status: Single

Nationality: Indian

Languages known: English, Hindi and Gujarati

References: Dr. N M Devashrayee & Dr. N P Gajjar

Contact this candidate