Design Engineer Computer Science
Resume:
Address ****F, Woodmar Dr, Houghton, MI, *****
Email *****@***.***
Cell phone 906-***-****
HomePage
Zhaoxiang Jin https://sites.google.com/a/mtu.edu/max jin home page/
OBJECTIVE
To obtain a full time position in the field of computer science or electronic engineering with focus on
computer architecture or ASIC design
EDUCATION
Michigan Technological University Houghton,MI
Master of Computer Science GPA 3.9
2012-
Familiar with computer architecture especially SuperScalar Processor
●
Expected 2014
● Complete the paper “Early Physical Register Release by Coloring”,
one innovative mechanism to mitigate the pressure of physical register
file by pre release the name before the retirement
● Modelize the L1 instruction cache and unified L2 cache
● Teaching Assistant for Java programming
● Parallel programing language like CUDA
● Advanced data structure and algorithm
● System programming with C in Linux
● Hand on experience for industry known simulator, SimpleScalar, Wattch, Cacti
Fudan University Shanghai,China
Master of Electronic Engineering GPA 3.24
2008-2011
● Thesis “A new design method for FPGA packing algorithm”
Duplicate the blocks in FPGA to shorten the critical timing path
Sun Yat-Sen University Guangzhou
Bachelor or Electronic Engineering China
● FFT implementation on Xilinx FPGA
GPA 3.1
● 8 bit microcontroller on Xilinx FPGA, compatible with the PicoBlaze
2003-2007
● VGA controller design to visualize the character on screen
● SOC projects with both software and hardware development on 8051
WORKING EXPERIENCE
Fairchild Semiconductor Shanghai,China
Digital Design Engineer 2010-2012
● Patent “One wire oscillator free communication protocol”
● Clock management with asynchronous wake up function
● Post layout multi corner, multi mode(MCMM) timing analysis
● DFT with scan chain across multiple clock domain
● Generate the entrance for test mode with shared pins
● Test pattern generation with ATPG and coverage analysis
● Mobile Power Solution like USB charger, LED driver, power switcher
● Hand on experience with oscilloscope to testify high current system
Sino Wealth Electronic Shanghai,China
Digital Design Engineer 2007-2010
● System integration, the whole system include the 8051 CPU, DSP, SRAMs,
ROM, multiple vector function units, peripherals and analog part
● Asynchronous design methodology with hand shake protocol and FIFO
● Algorithm implementation with verilog like IDCT, BCH, 5 bit ECC
● Innovative programmable NAND Flash controller
● FIB experience to debug the sample chips
● Whole system evaluation with FPGA including high speed USB Phy
LEADERSHIP
2008-2010
● Design Leader, in charge of all the design phases through the project
make up the schedule, cooperate with the different departments, manage
the human resource, product test and yield
SKILLS
Register rename Branch predictor Continual flow pipeline SRAM
Verilog Simulation Sythesis STA Formal verification OTP
CUDA C & Java FPGA Layout Assemble language ROM
ECC CVS TCL ChipScope Linux PLL Latex
LANGUAGE
● Mandarin native language
● English able to give a lecture for the classes
VOLUNTEER
2012-2013
● EWB (Engineers Without Borders) member
REFERENCE
Dr Soner Onder, Associate Professor
Michigan Technological University
Department of Computer Science
303 Rekhi Hall, *****@***.***
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