Data Power

Bhavya Nannapaneni

Contact Plot No-***, Voice: +91-800**-*****

Information Vasanth Nagar Colony, Fax: NA

Hyderabad 500072 E-mail:****************@*****.***

Andhra Pradesh, India.

Research 1. Low Power VLSI

Interests 2. Nano Robotics

Education 1. Bachelor of Technology (B.Tech), Electronics and Communica-

tion Engineering (ECE)

Vardhaman College of Engineering, affiliated to Jawaharlal Nehru

Technological University (JNTU-H) Hyderabad, India, 2014 (expected)

77%

2. +2 Intermediate Public Examination(IPE), 2010 with 92%

3. Secondary School of Certificate(SSC), 2008 with 83%

Honours and 1. Cadence VLSI Certification Program-2013, certified by Cadence Design

Awards Systems, Bangalore with 73%

2. Presented papers on ”Eye robot” and ”Blue brain” in a National level

Techinal Symposims at VNR VJIET in 2012.

3. Won Merit prize in Quiz-viz in my B .Tech degree.

4. Organized a ROBOTIC event ”ROBO Maze” in National level Student’s

Technical Arena (Technolites) VCE, 2013.

5. Worked as a coordinator in Cultural fest ORTUS (VCE) in 2013

6. Organized a Technical event ”Satellite house” in Technolites 2k13, VCE

7. Participated and won Merit in drawing competition 2004.

Projects 1. Full and Semi Custom Digital Implementation of CRC(3,5

Team Members: Bhavya, Manisha, Srilaxmi, Vaishnavi..

Description:The cyclic redundancy check, or CRC, is a technique for

detecting errors in digital data, but not for making corrections when

errors are detected. It is used primarily in data transmission. In the

CRC method, a certain number of check bits, often called a checksum,

are appended to the message being transmitted. The receiver can de-

termine whether or not the check bits agree with the data, to ascertain

with a certain degree of probability whether or not an error occurred

in transmission. If an error occurred, the receiver sends a ”negative

ac- knowledgement” (NAK) back to the sender, requesting that the

message be retransmitted. The technique is also sometimes applied

to data stor- age devices, such as a disk drive. Crc5 is used in USB.

Crc is implemented using linear feedback shift registers(LFSR’s). At

transmitter encoder is a parallel in sipo(serial in parallel out) circuit.

For crc5 highest degree of generator polynomial is 5,no of ip ops is

equal to highest degree of generator polynomial. Message bits are

send serially to LFSR,for each message bit remain- der is obtained,

the remainder which is obtained for the last message bit is called as

checksum bits. At receiver end these checksum bits are appended to

message and then retransmitted through LFSR if the re- mainder ob-

tained atlast is equal to zero then there is no error if the obtained

remainder is a non zero number then we say that error has occurred

in the transmission of data. D-FFs are used for LFSR for this layout

is drawn by using cadence virtuoso tool.

2. Square Rooting by Convergence

Team Members:Bhavya, Manisha.

Description: The algorithm of estimation and compensation of er-

ror effects for rounding in the case of implementation of square root

using Newton raphson method. We analyse the error of the hardware

system to conform the condition of the implementation with respect

to this algorithm. The number of increasing cycles for this algo- rithm

is only one .This is typically used to find the root of particular num-

ber. This requires the derivative function to be evaluated, hence more

function evaluations per iteration. Each iteration consists of three op-

erations namely divi- sion, addition and single-bit shift. The hardware

consists of registers, divider, adder, multiplexer. The exact square root

of a given number is determined when the value meets the number of

digits specified by the user. This is implemented using ieee 2001 ver-

ilog code, simulated using ncverilog and synthesized using encounter

rtl compiler.

3. Area Optimized Low Power High Speed 14-Transistor Full Adder

Team Members:Bhavya, Vaishnavi.

Description: Full adders are important components in applications

such as digital signal processors (DSP) architectures and microproces-

sors. In addition to its main task, which is adding two numbers, it

participates in many other useful operations such as subtraction, mul-

tiplication, division, address calculation,..etc. In most of these sys-

tems the adder lies in the critical path that determines the overall

speed of the system. So enhancing the performance of the 1-bit full

adder cell (the building block of the adder) is a significant goal. De-

mands for the low power VLSI have been pushing the development

of aggressive design methodologies to reduce the powerconsumption

drasti- cally. To meet the growing demand, we propose a new low

power adder cell by sacrificing the MOS Transistor count that reduces

the serious threshold loss problem, considerably increases the speed

and decreases the power when compared to the static energy recovery

full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell

is presented in this paper. Results show 50% improvement in thresh-

old loss problem, 45% improvement in speed and considerable power

consumption over the SERF adder and other different types of adders

with comparable performance.

Study Projects

1. Design and implementation of High level Data link controller

by using Cyclic Redundancy Check.

Team Members:Bhavya, Zubair Basha

Description:To transmit and receive data at high speed in any net-

work without any error a protocol is required. HDLC protocol of

layer- 2 of OSI model which is most suitable for bit oriented packet

transmission mode High-level data link control (HDLC) is a bit ori-

ented data link protocol designed to support both half-duplex and

full-duplex communication over point-to-point and multipoint links

and switched and non switched channels. It is developed by Interna-

tional Organization for Standardization. Another benefit of using this

protocol is that the control information of the received or transmitted

data is at same position and in specific bit pattern but differ from the

data which reduces error. System Description: The HDLC protocol

transceiver consists of the following main blocks Control unit and Reg-

isters, The Transmitter,The Receiver, RAMS and RAM management

unit, Interrupt Controller.

2. Ultra Bright and Energy Efficient Nano Light

Team Members: Bhavya, Srilaxmi.

Description A new LED lightbulb that is the most energy efficient on

the planet. The NanoLight takes energy efficient lighting to the next

level. Using only 12 watts of electricity, it generates over 1600 lu-

mens. This allows for light to be distributed evenly. Unlike compact

uorescent lights, the NanoLight achieves full brightness the instant

it is turned on. Most LED light bulbs or CFL’s have a problem of

overheating within a fully enclosed fixture, which causes the LEDs to

start failing well before their expected lifetime. The reason for this

is that these fixtures do not allow for sufficient air ow, thus trapping

the heat inside and overheating the bulbs. We can- not claim that the

NanoLight will work in absolutely all enclosures, but we can say that

the NanoLight emits less than half the energy as compared to other

LED bubs or CFLs. The chance of overheating is far lessened. If the

bulb gets too hot for whatever reason, it will automatically dim itself

to prevent damage or shortened life.

Computer 1. Hardware Description Language :Verilog

Skills 2. Programming Languages : C

3. Operating Systems : Windows, Linux

4. Scripting Languages : Basics of Tcl scripting.

5. Tools: Matlab, Multisim, NC, Spectre, Virtuoso ADE, Assura, En-

counter RTL Compiler, SOC-Encounter.

Personal Name : N.Bhavya

Details Mother’s Name : N.Sarala Kumari

Father’s Name : N.A.Chowdary

Date of Birth : 16-Mar-1993

Hobbies : Chess, Cooking.

Languages : English, Telugu, Hindi.

Bhavya Nannapaneni

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