Resume
Manjunath T N Career Objective
Polisetty
*********@*****.*** To pursue a challenging position in a semiconductor
Mobile: 888******* company, where my professional and technical skills can be
put to maximum use and contribute towards the growth of
Technical Skills the organization and personal development.
RTL
Simulation Qualification
Synthesis
Timing Analysis M.Tech Project Training Program (MTP) in VLSI System
Design from M.S.Ramaiah School of Advanced Studies,
Bangalore.
HDL: M.Tech in VLSI Design and Embedded system (80%) from
Verilog, SSIT,Tumkur - 2014.
B.Tech in Telecommunication (59.4%) from P.A collage(VTU),
Scripting: Mangalore- 2012.
Dipolma in Electronics and commuication (60%) from SPT,
Tumkur - 2009.
Areas of interest EDA Tools
ASIC Design
FPGA Design Simulation Tools : ModelSim, Ncsim.
Digital design using Synthesis Tool : Xilinx ISE, RTL Compiler.
Verilog HDL STA Tool : Encounter Timing System.
Verification Tool : RTL Encounter TEST
Strengths
Personnel Details
DOB: 13-12-1989 Exposure to EDA Tools.
Nationality: Indian Knowledge in verilog.
Marital Status: Single Self motivated.
Good presentation and communication skills.
Languages Known:
English, kannada, and
Hindi.
Title: Design & Development of JTAG For Trace and Debug of
Hobbies: Traveling, Controller and Implementation on FPGA.
Cricket.
Tools: ModelSim, Xilinx ISE v 13.1.
Present Address: FPGA Board: VERTEX-5.
B.M TANUJALAKSHMI S/O
MANJUNATH T.N 6TH MAIN Description:
3RD CROSS In this project RTL level code (Verilog) was designed by
SADASHIVANAGAR using FSM (Mealy) and is simulated in ModelSim and the
TUMKUR-572102 functionality of the design is verified. Now the code is
given as input to the Xilinx ISE tool to implement the
design in VERTEX-5 kit. The Area, Power and Timing of the
designs are compared, to come out with an efficient
design.
Declaration
I here by declare that the above mentioned particulars are
true and correct to the best of my knowledge and belief.
Place: Tumkur (TN.
Manjunath)