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Engineer Design

Savannah, Georgia, United States
March 07, 2014

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Keith R. Long

** **********, ******** **. ***** H: 315-***-****

Objective: Sr. Engineering position in an ASIC design team.

Profile: Over 19 years of CMOS design experience concentrated in 100 plus SONET

and BROADBAND ASIC architectures. The scope of ASIC design comprised PD,

digital test, functional & topological verification, DFT - test insertion, timing

closure via STA & vector simulation, and SI. Strong analytical and result oriented

objectives emphasizing development and execution. Skillful script manipulation

augmenting CAD tools’ utility and ease of use to deliver production ready IC’s.


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STA PWR/CLK Routing Strategies

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Vector Verification Working with design team to meet our objectives.

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Analog Sim/Eval Communicate with customers defining product details.

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Digital Test Script Automation

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Testability-Scan/BS Strong Unix background and Office Tools

Professional Experience:

LSI, Signal Integrity Engineer (MTS) 3/2009-12/2012

Serving signal integrity for DDR2-3 memory interface. This work included HSPICE

realization from SOC-PKG-PCB-MEM and back. Models used: HSPICE and IBIS.

Work also focused on jitter analysis and DCAP recommendations. ODJ the major

component of clock jitter was extensively observed under various power distribution

schemes, operating conditions and process variations.

SI sign off on TSMC’s 40nm technology implementing a 1067MB DDR2 interface.

Assignment Details Included:

-IO planning and placement guidelines during early phase of SoC design.

-Estimation of on-die decoupling requirement for particular design.

-Provide guidelines for IP integration within SoC.

-Engagement with package bonding team on bump & ball pattern for optimum routing.

-Work with package/board layout engineer and provide routing guidelines.

-Evaluate timing jitters parameters effecting timing margins (PLL jitter, clock tree jitter,

skew, HM jitter etc.) within Co-simulation environment.

-Spice deck automation and measurement scripting solutions for more efficient


-Developing SI, PI methodology including package, board, memory module modeling,

-SSO methodology, on-chip parasitic modeling, correlation between lab measurements

& simulation and providing feedback to software vendors in order to refine software

tools and extraction methodology.

-Develop IP including SSO simulation with I/O, package and loading to verify setup,

hold timing margins and other SI specifications.

-Tests chip board development, perform test chip board review and post route

simulations in order to develop board design guidelines

-Customer support duties include HSPICE SSO simulations using custom package

models, performing feasibility studies, topology verifications.

-Assist customers with debugging SI failures; finding root causes and offering

solutions to solve issues.

PMC-Sierra, Senior Product Design Engineer 1/2000-10/2001

Functioning as testability expert administering SCAN and BS/JTAG in ASIC designs.

Scan imposed overwhelming test equipment demands including time to test. Effort to

minimize testability’s impact on re-occurring cost, a top down modular approach was

employed. The test comprised 54 chains through 18 levels of hierarchical sub networks

containing 100k+ FF’s to be joined on exit via XNOR logic. Vector input stimulus via

Mentor’s Tessent ATPG tool was employed and the compare or chip I/O strobe is always

one, except during toggle test. Test insertion was completed for two devices bound for

production in a subsequent release.

Lucent Technologies, Product Design Engineer (MTS) 1/1992-12/1999

NETCOM/Broadband ASIC Department design responsibilities included

communicating with customers to define or re-define SoC requirements to implement and

verify gate level designs. The process comprised circuit topology audits-ALERT, vector

simulation-VERILOG-IKOS-EMU, STA –TACO-PRIME TIME, transistor level simulations

- ADVICE -CELERITY. Test insertion was also employed using Tetramax (Synopsys)

and Sunrise for SCAN insertion and BCAD to include BS/JTAG.

Close interaction with layout and test engineers providing guidelines of each ASIC.

Communication with marketing and product engineering for customer and manufacturing

needs, supporting multiple projects at same time.


-ECHO CANCELER (10 million transistors), that included several generations of technology.

added testability, designed an innovative memory interface for higher performance, hands

on performance optimization, floor planning, layout interface, test interface and

manufacturing support.

-STAR ASIC (Satellite Communication device), Standard backend design verification to

include Celerity simulations and validation for a DDL (Digital Delay Line), developed

vector stimulus, test bench and analog/digital test program. Device yield was

significantly improved.

-SMAX (Gallium Arsenide to CMOS) Transistor level design of a pseudo ECL Buffer for a

Custom Application used in Schlumberger’s test equipment.

-Received numerous Spot Awards (35+) in recognition for proficient execution.

Lucent Technologies, Senior Technical Associate (STA/TA)


STA and TA responsibilities focused in silicon layout and test support.

Employed LTX2 for layout and floor planning, successfully completing numerous

complex, mix signal and mix voltage ASIC’s meeting: IO-SPECS, clock skew, and

timing convergence, and power distribution; maintaining schedule.

Digital test engineer responsibilities included interfacing with designers, product

engineers and customers. Test generation initiated by TPG2 evolved through debug,

specific device requirements and AC/DC characterization. Production ready test

programs were delivered for TEKADA test equipment. In the event of high production

drop out; test programs were re-analyzed for yield improvement.

Educational/Technical background:

Associate Degree in EET (3yr) Hudson Valley Community College, Troy, N.Y.

Training Courses in Synopsys, Primetime, Boundary Scan, Verilog, IKOS,

Celerity, Advice, Mentor, HSPICE, etc.

Key Words:




References: Will be furnished upon request.

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