Project Information Technology

K.L.Prasanna

D/O.K.Thirupathaiah,

Inamanamellur(vi),

Maddipadu(M.D),

Prakasam(Dt), E-mail: ****************@*****.***

Pin Code - 523211. Contact No: +91-893*******

OBJECTIVE:

To become a successful professional in the field of Information Technology and to

work in an innovative and competitive world.

ACADEMIC PROFILE:

Qualification Institution Board/ Month &Year Percentage/

University of Passing CGPA

M.Tech(Pursuing) Sathyabama Sathyabama April, 2014 7.8(CGPA)

VLSI DESIGN University, University,

Chennai. Chennai.

B.Tech Rao&naidu JNTUniversity, April, 2012 65.08

(Electronics and engg. College Kakinada

Communication

Engineering)

Intermediate, Sripratibha Board of May, 2008 78.1

(MPC) Jr.Colleg, Intermediate

Ongole Education, A.P

SSC PVChigh Board of May, 2006 75.5

School Secondary

Maddiralapadu Education, A.P

TECHNICAL SKILLS:

Operating Systems : Micro wind 2.1, P-spice, Tanner EDA, Xilinx.

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Languages : C, C++,Core VHDL, VERILOG,HDL.

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RELEVANT SKILLS:

Excellent Advanced Embedded system skills.

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Excellent Program designing skills.

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Good Internetworking skills.

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EXTRA CURRICULAR ACTIVITIES:

• Presented a project on device controlling through pc at QIS CET

• Organizer of various technical and cultural fests in our college.

M.TECH ACADEMIC PROJECT:

Title : High performance of dual dynamic flip-flop using Combinational Circuits.

Software : Tanner

Technology : S-edit

Description : The proposed designs eliminate the large capacitance present in the pre-

charge node of several state-of-the-art designs by following a split dynamic node structure to

separately drive the output pull-up and pull-down transistors. This project is basically used

for less complex and reduced power circuits. Achieves high speed operation through

pipelining function. Area and Delay decrease.

B.TECH ACADEMIC PROJECT:

Title : Design and Implementation of FPGA based on Face Recognisation.

Software : VHDL

Technology : Xilinx9.2ISM, Modelism 6.4.c

Description : This project is used basically Recognisation of different face images. The

enhancement is increased. The pixel also reduced. This system consists of three subsystems:

face detection, down sampling and face recognization.All of the modules are designed and

implemented on a virtex-5 FPGA.

STRENGTHS:

• Leadership Quality

• Hard working and has zeal to learn new things.

• Optimistic in nature.

PERSONAL PROFILE:

Name : K.L.Prasanna

Father’s Name : K.Thirupathaiah

Nationality : Indian

Date of birth : June 27, 1991

Language’s Know : Telugu,English,Tamil

DECLARATION:

I hereby declare that the information furnished above is true to the best of my

knowledge.

Place: Chennai

Date: K.L.Prasanna

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