Engineer Project Manager

BRIAN ANDRADE GABARDA

Blk ** Lot * Cerritos Heights, Camella, Daanghari, Molino IV, Bacoor,

Cavite, Philippines

Contact Numbers: +639*********

Email Address: ********@*****.***

Passport #: EB2488523 US VISA Class: R B1/B2

FIN #: G5252633M

QUALIFICATION SUMMARY:

Practical Experience with project management for high-speed PCB Design for

multi layer Test Boards. Process ownership for ATE boards, from design

kickoff, to schematic, layout and fabrication with assembly. Work is not

limited to design and PCB house supplier qualification, Quality Audit and

monitoring for PCB suppliers but includes Supplier assessment and pre

qualification check, RFQ and supplier quarterly feedback.

SYSTEMS HANDLED:

- CADENCE ALLEGRO 16.5

- Mentor Graphic PADS V9

- Altium Designer 10

- CAM350/GC preview/Viewmate Gerber Viewer

- Cadence Virtouso, Hercules

- Proficient in Microsoft Office such as Word, Excel, Power Point

Presentation, etc.

RELATIVE EXPERIENCES:

CURRENT POSITION:

Sr. Test Hardware Engineer

Microchip Technology Inc. (January 2013 - Present)

Responsibilities: Project Manager

< Creation of full ATE Hardware Design for the product test fixture

based on the project definition and participates through out the

development cycle as a member of the team. The team includes

representatives from Test Hardware Development, Contractors, Product

Engineering, Test Engineering and Test Hardware.

< Full ownership in transferring of design to in-house as part of cost

efficiency initiatives, especially for new acquisitions of the

company.

< Responsible for PCB supplier qualification, handling NDA, survey form

and RFQ evaluation.

< Handles project definition and scheduling, PCB Layout design, working

with various external suppliers, leading the technical teams and

project management.

< Working with the Test Hardware Engineering groups to create schedules

and expectations for work deliverables.

< Participates in the design reviews and providing the PCB layout files

for the review meetings at critical points in the development process.

< Responsible in Assembly area monitoring and conduct assembly inspection

after built

< Technical participation and provides support to other groups within the

team for hardware requirements such as wireless group, automotive and

manufacturing/production

< Tester hardware familiarity on J750, Eagle, TTS, Nextest Magnum, Fusion X

series and LTX diamond.

< Experience on various handlers such as Rasco, Multitest, Ismeca, Simeca,

Microflex, Ultraflex, NS8080, Delta Castle and Delta Edge

PREVIOUS POSITIONS:

Sr. Hardware CAD Engineer

Microchip Technology Inc. (October 2007 - January 2013)

Responsibilities:PCB Design for ATE Boards

< Part of the pioneering team for Microchip Technology Inc.'s Philippine

operation that started on October 2007 and is responsible for setting up

the group of Test Board CAD for test engineering that supports all

products.

< Responsible for Library Creation Guidelines and Template Creation for CAD

design

< Involved in Quality Audit and visits for potential PCB supplier

< Monitoring PCB vendor for cycle time and manufacturing issues.

< Develop and analyze data for RFQ process

< Evaluate product flow times and develop/implement improvement plans

< Completed at least 10 complicated board layout per quarter as part of

individual goal set

< Designs multilayer boards from 20-40layers of ATE boards for J750 tester,

Striptest, Multitest, Microflex, Eagle test boards and probe cards

< Complex RF ATE boards

< PADS 2005-PADS V9 with Router, verification and checking, documents and

deliverables generation, gerber generation and direct communication for

PCB fabrication house.

Hardware CAD Engineer

EAZIX-IMI Phils. Inc. (November 2005 - September 2007)

Responsibilities: RnD PCB DESIGN

< Responsible on complete development of CAD layout from symbol creation,

floor planning and detailed component placement, through constraints

management, with a concept of topology and signal/trace integrity where

designs release require generation of Gerber files, ODB++, test reports,

and electronic PCB documentation

< Project management such as preparation of system requirements for

Customer, Project Management Plan and Date scheduling using Gantt chart

(MS project), Technical Plan, DFMEA, and Internal to external customer

communication for technical issues, conduct conference meeting with

foreign counterpart and customer.

< Experience on PCB for high speed/controlled impedance transmission line

design. RF pcb design for WIFI, Bluetooth and Zigbee

< Design modular board with European standard for automotive and commercial

products.

< Familiar with the IPC standard for footprint creation

< Exposure to full product design life cycle

< Review and revise PWB office documents to adapt new rules and ideas

< Used cadence allegro 15.7/ 16.0 for PCB design, responsible for

documentation such as Fabrication Notes, checklist, report, DFM, DRC,

GERBER FILES, films

Physical Design Engineer (IC Layout Engineer)

Intel Philippines (April 2004 - March 2005)

Responsibilities: Physical Design Engineering

< Responsible for schematic to cell layout design methodologies in

fabrication of wafer products (flash memory) using Cadence virtouso

software(VLSI, LSI)

< Floor planning, device placement, routing, verification and continuous

support for foreign counterpart

< Conduct internal training and seminar within the group for design

improvement

< Consistent layout and constantly beat the deadlines with good

interpersonal skills with the foreign counterpart (Shanghai and Folsom)

< Familiar with industry standard layout editors, DRC and LVS, metal

density and antenna check. ( virtuoso)

< Using Exceed and Hercules tools for Verification with Unix (Solaris and

linux) base software.

Associate Design Engineer

Phils. EDS Techno-Service (YASAKI Design Group) (November 2003 - April

2004)

Responsibilities:

< Bench marking of different car wiring harness for design improvement

< Documentation and drawing using MS Office and HCAD

EDUCATIONAL BACKGROUND:

DEGREE#1: Bachelor of Science in Electronics and Communications

Engineering

Jan 1998 - May 2003 (Graduated)

Polytechnic University of the Philippines

Major in Digital Electronics

DEGREE#2: Masters of Science in Electronics and Communications

Engineering

July 2006 to present (Undergraduate)

Mapua Institute of Technology

Major in Microelectronics

PERSONAL INFORMATION:

Religion : Roman Catholic

Age : 31 years old

Birthday : May 14, 1981

Height : 5'4"

Weight : 150 lbs.

Civil Status : Married

CHARACTER REFERENCES:

Available upon request.

I hereby certify that the above information is true and correct to the best

of my knowledge and belief.

Brian A. Gabarda

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