GUOQING (MAX) DENG

* * ****** *** *****, Markham, ON, Canada L3P 3H8

Cell: (647) 983 – 5088 Email: acbz8u@r.postjobfree.com

HIGHLIGHTS OF QUALIFICATIONS

Solid academic background in Analog/RF/Mixed-Signal IC design.

Experienced in CMOS analog design, including op-amp, PLL, delta-sigma ADC.

Experienced in CMOS ASIC design flow through Cadence and Synopsys.

Skilled in Perl and Cadence SKILL scripting in Linux environment.

Good at C, C#, Excel VBA, Verilog HDL, Labview, Matlab programming.

Good at hardware testing / debugging using oscilloscope, functional generator, etc.

Creative and enthusiastic individual with strong work ethic and interpersonal skills.

WORK EXPERIENCE

Jan. 2013 – Present

AMD, Markham, ON, Canada

Senior Analog Engineer

Porting standard cell libraries from GF20LPM to TSMC16FF, and then to GF14XM.

Schematic optimization and Layout validation in Cadence Virtuoso for standard cell

libraries in TSMC16FF and GF14XM.

Hspice / Spectre monte-carlo simulations for flops in TSMC16FF, including race margin,

charge sharing, meta-stability, and setup / hold time analysis.

Extensive Perl and Cadence SKILL scripting for design automation.

Jan. 2012 – Jan. 2013

KSR International Co., Ridgetown, ON, Canada

Electronics Product Engineer

Developed system specifications for a digital inductive position sensor which includes LC

oscillator, Gilbert cell, delta-sigma ADC, FIR filters, EEPROM, etc.

ASIC hardware testing on PCB board using oscilloscope, multimeter, functional generator,

impedance analyzer, etc.

Labview programming for data acquisition.

Excel VBA programming for data analysis.

PSpice simulation using Altium Designer.

Aug. 2006 – Aug. 2007

Suzhou Galaxy Camphol Tech. Co. Ltd., Beijing, China

Electrical Engineer

PLC programming using C language for a LCD meter controller.

Windows application programming using C# language in Microsoft Visual Studio, including

the use of Microsoft Access Database.

EDUCATION

Sept. 2007 – Oct. 2011

University of Windsor, Windsor, ON

PhD in Electrical and Computer Engineering

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Arithmetic circuit design for low-power applications using MOSFET and Single-Electron

Transistor (SET) in Cadence analog environment.

Graduated Courses (GPA: 11.5 / 12 or 3.9 / 4):

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VLSI Design Digital Signal Processing

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Advance Analog IC Design Data Security & Cryptography

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RF Integrated Circuit Design Advanced Topics in MEMS

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Mixed Signal IC Design Introduction to Nanoelectronic Design

– –

Low Power CMOS Design Reconfigurable Computing

– –

Solid State Devices Computer Arithmetic

Academic Projects

– Designed a fully differential Op-amp with unity gain frequency of 200MHz using 0.18µm

CMOS technology in Cadence.

– Designed a charge-pump PLL with center frequency of 1.6GHz, including system-level

prototype using Verilog-A and transistor-level design using 90nm CMOS technology in

Cadence. The phase noise of designed PLL is 100dBc (with 400KHz offset frequency).

– Designed an 8-bit radix 4 booth algorithm multiplier using 90nm CMOS technology,

including layout design for logic gates using Cadence Virtuoso, Verilog coding and

synthesizing, code / gate level simulation using Cadence NCSim, and static timing

analysis and power estimation using Synopsis Prime Time.

– Capacitive Micromachined Ultrasonic Transducer (CMUT) design, including analytical

modeling using Matlab, 3D finite element analysis and CMOS fabrication step simulation

using IntelliSuite.

– Software FIR filter design using W indow Techniques in Matlab.

Sept. 2004 – Jul. 2006

Beijing Institute of Technology, Beijing, China

Master in Electromechanical Engineering

PLC programming using C language for a signal emulator system.

Sept. 2000 – Jul. 2004

Beijing Institute of Technology, Beijing, China

Bachelor in Electromechanical Engineering

CPLD programming using VHDL for a data acquisition unit.

ACTIVITIES

Attended the 11th IEEE International Conference on Nanotechnology for the Oral

Presentation in Portland, Oregon, Aug. 2011.

Attended the 10th IEEE International Conference on Nanotechnology for the Poster

Presentation in Seoul, Korea, Aug. 2010.

Attended the 1st Microsystems and Nanoelectronics Research Conference for the Poster

Presentation in Ottawa, Canada, Oct. 2008.

PUBLICATIONS

G. Deng and C. Chen, “Binary Multiplication Using Hybrid MOS and Multigate Single-

Electron Transistors,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,

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vol. 21, no. 9, Sept. 2013, pp. 1573-1582.

G. Deng and C. Chen, “A SET/MOS Hybrid Multiplier Using Frequency Synthesis,” IEEE

Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 9, Sept. 2013,

pp. 1738-1742.

G. Deng and C. Chen, "Hybrid CMOS-SET Arithmetic Circuit Design using Coulomb

Blockade Oscillation Characteristic," Journal of Computational and Theoretical

Nanoscience (JCTN), vol. 8, no. 8, Aug. 2011, pp. 1520-1526.

REFERENCES AVAILABLE UPON REQUEST

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